Evaluation of SOFIST1 by TCAD simulation R.Tsuji (Yamanaka Lab.) - - PowerPoint PPT Presentation

Evaluation of SOFIST1 by TCAD simulation

R.Tsuji (Yamanaka Lab.) 2015/12/25th year-end workshop@Osaka Univ.

1

Contents

• ILC Experiment
• SOI Technology
• The SOI Pixel Sensor, SOFIST1
• The Estimate of the Full Depletion Voltage
• Cross Talk
• backgate effect (circuit <- sensor)
• sensor potential (sensor <- circuit)
• Psub/Psub (one pixel <- one pixel)
• (Charge Sharing)
• Conclusion

2

central region 5 km 2 km positron main linac 11 km electron main linac 11 km 2 km Damping Rings e+ source e- source IR & detectors e- bunch compressor e+ bunch compressor

ILC

• International Linear Collider
• linear electron-positron collider
• 200 ~ 500 GeV in C.M. 


(1 TeV in the future)

3

total length ~31km

SiD detector (parked) ILD detector (on beamline) ILD garage

One of ILC’s Purposes

• ATLAS and CMS found the particle, “Higgs”
• precise measurement of Higgs properties
• LHC experiments has many backgrounds (pp

collision)

• electron-positron collider has less backgrounds

4

We can measure the precise measurement at ILC Our group struggles to make a chip of the vertex detector for ILC

Requirement to Sensor

5

• sensor size: 10mm x 125mm (max)
• spatial resolution: less than 3um
• low amounts of matters: (sensor thickness) < 100um
• pixel occupancy: less than 2%

AcVve$area$ 6250(H)×500(V) pixels$

• 125mm

10mm

8bit$ADC$×$6250ch$ (TBD)$Digital$memory$(SRAM?) Controller$ (Timing/Readout/Memory/Output) Data$transmission$interface Data$output$(parallel?)

• 20um

??mm

10mm 125mm

SOI Technology

• Silicon On Insulator
• sensor and ASIC in a chip
• monolithic pixel detector
• NO bonding

6

図 の断面図。下部の 型基板をセンサーとして使用する。

の利点

で述べたように、 技術を半導体検出器に応用すると様々な利点が生まれ る。本節ではそれぞれの利点について詳細を述べる。 高速性 トランジスタは トランジスタよりも、ソース、ドレイン 領域の接合容量が絶縁膜によって大幅に低減する。寄生容量が減少することにより、 高速な読み出しが可能である。 低消費電力 回路は絶縁膜によってシリコン基板部と回路部が絶縁されている為に リーク電流が減少する。これにより、消費電力を抑えることが出来、大量に検出器 が導入される実験では電源系、冷却系の負担が減る。高エネルギー加速器実験では、 内層に冷却用のパイプ等の不要な物質を減らすことが出来る等の利点が挙げられる。 また、電源の限られている宇宙関係、人工衛星等に載せて行う実験では消費電力の 低下は大きな利点となる。

Active area 50×50 pixels 8bit column ADC × 50ch

20um

Row selector Bias circuit Column selector

Output data (8bit)

Ramp Generator

SOFIST1

• SOi for Fine measurement of Space and Time Ver.1
• this version is the prototype
• 1pixel size : 20u x 20u
• Column ADC readout
• Controlled by SEABAS
• without a discriminator 


and circuits for time stamp

• I worked on 


the pixel architecture
 and the layout

7

Pixel Architecture

8

大本・今村

ピクセル構成 案

PD Pre-amp

RST STORE1 STORE2

Multi-buffer

READ1 COL_OUT

ピクセル回路への追加予定

• リセット電圧入力
• テスト信号入力

READ2

大本・今村

試作チップの

5f 100f

• referring to the circuit of XRPIX
• I checked this circuit worked well, simulating it

TCAD Simulation in 2 Dimensions

• Estimate of Full Depletion Voltage
• Cross Talk
• Backgate Effect (transistor <- Sensor)
• Potential in the Sensor (transistor <- Sensor)
• Psub/Psub (pixel <- pixel)
• (Charge Sharing)

9

Sensor Basic Structure For TCAD

10

Circuit layer SiO2 layer Sensor layer 50um 0.2um 0.04um 20um Vbias

Psub (P-type)

10um 60um

BPW N-type X Y

11

Circuit layer(SiO2) SiO2 layer Sensor layer Vbias

Estimate of Full Depletion Voltage(BPW14um)

BPW14um Density of electrons VS Sensor depth(0 <= Vbias <= 100) V=0 V=0 V=0 —>

12

Density of Electrons

Vbias = 0V Vbias = 5V Vbias = 60V Vbias = 80V Vbias = 40V Vbias = 20V

e- density vs sensor depth

13

Probe_Xm10_Ym0c0tom50c0.dat

Probe_Xm0_Ym0c0tom50c0.dat

Probe_X10_Ym0c0tom50c0.dat

Probe_X20_Ym0c0tom50c0.dat

Probe_X30_Ym0c0tom50c0.dat

Probe_X40_Ym0c0tom50c0.dat

Probe_X50_Ym0c0tom50c0.dat

Vbias = 20V Vbias = 40V Vbias = 30V Vbias = 100V Vbias = 60V Vbias = 50V Psub Psub Psub Vdep ~ 50V

14

Circuit layer SiO2 layer Sensor layer Vbias

Cross Talk(transistor <- sensor)

Id Vg=0V Vs=0V (Vd=1.5V) Id vs Vbias (w/ or w/o BPW) BPW14um BPW exists to shut the cross talk(transistor <- sensor)

15

−10 10 20 30 40 50 60 70 80 90 100 110

V VBack

1e−15 1e−14 1e−13 1e−12 1e−11 1e−10 1e−09 1e−08 1e−07 1e−06 1e−05 0.0001 0.001

A IDrain

GraphIV2

::2D_NFZ50um_NIO_Tr_backgate_dtr10um_cur.Condition0−VBack−IDrain ::2D_NFZ50um_NIO_Tr_backgate_dtr10um_BPW_cur.Condition0−VBack−IDrain

Vbias [V] Id [A] w/o BPW w/ BPW 100 1e-13 1e-4 1e-9 BPW surely shuts backgate effect

How length can transistor protrude from the edge of BPW?

• BPW 14um
• I placed a transistor from away the BPW edge by

0u, ±0.5u, ±1.0u,,,,,,

16

17

V VBack

A IDrain

GraphIV17

−2.0um −1.5um −0.5um 0.0um 0.5um 1.0um 1.5um 2.0um 3.0um

Vbias [V] Id [A] 2.0e-13 0.0 1.0e-13 0.0 100 50

<— on the edge of BPW <— on the center between 2 Psubs

this value << ~4e-7A (the drain current @ operating point of the NMOS)

10 − 10 20 30 40 50 2 4 6 8 10 12 14

Graph

Potential in the Sensor at the Sensor/SiO2 interface

18

X [um] Potential [V] w/o BPW BPW 12um BPW 14um BPW 16um Vbias = 50V

19

Vbias = 50V

Charge Sharing(BPW14u)

V0= 0.5V V1 = 0.5V V2= 0.5V 14um

• 4.5um
• 49.5um

1980 pairs

+ + +

• simulating, shifting by 1um

(0,0)

20

t = 1e-12 t = 1e-11 t = 1e-10 t = 1e-9 t = 1e-8 Charge is generated at X = 0.0

e- density

21

−2.e−06 −1.e−06 0. 1.e−06 2.e−06 3.e−06 A IBack

I vs TIME IBack IPsub11 IPsub12 IPsub13

Time [s] I [A] 1e-6 1e-7 1e-8 1e-9 1e-11 1e-10 1e-12 1e-13

22

Table 1

Qback Ql Qc Qr X x0 4.00636E-16 4.38924E-18 4.09409E-16 4.38924E-18 2.12144E-01 x3 4.00654E-16 5.33682E-18 4.09619E-16 3.62904E-18 2.57224E-01 x5 4.00685E-16 4.42831E-18 4.08315E-16 3.20338E-18 2.14579E-01 x6 4.00702E-16 5.65918E-19 4.04304E-16 3.03817E-18 2.79555E-02 x7 4.00733E-16 1.47268E-17 3.88854E-16 2.85009E-18 7.29807E-01 x8 4.00767E-16 4.38866E-17 3.59591E-16 2.7132E-18 2.17542E+00 x9 4.00794E-16 1.15959E-16 2.87381E-16 2.54875E-18 5.74994E+00 x10 4.00798E-16 1.99087E-16 2.0413E-16 2.42163E-18 9.87493086849017E+00 x11 4.00789E-16 2.84951E-16 1.18128E-16 2.29377E-18 1.41387E+01 x12 4.00765E-16 3.55496E-16 4.74216E-17 2.15469E-18 1.76461E+01 x13 4.0073E-16 3.86781E-16 1.59852E-17 2.03797E-18 1.92062E+01 x14 4.00702E-16 4.01494E-16 1.12891E-18 1.92273E-18 1.99439E+01 x15 4.00686E-16 4.0614E-16 3.63175E-18 1.83095E-18 1.98227427830249E+01 x16 4.00671E-16 4.0739E-16 4.98459E-18 1.73691E-18 1.97582494110512E+01 x17 4.00659E-16 4.07336E-16 5.01789E-18 1.66121E-18 1.97566E+01 x18 4.0065E-16 4.07074E-16 4.83419E-18 1.59224E-18 1.97653E+01 x19 4.00642E-16 4.06775E-16 4.60951E-18 1.52501E-18 1.97759E+01 x20 4.00635E-16 4.065E-16 4.40007E-18 1.4677E-18 1.97858325991524E+01

Charge Sharing(BPW14u)

23

• Xcs = Q1/ (Q0 + Q1) * d (d = 20u)
• 20.0
• 18.0
• 16.0
• 14.0
• 12.0
• 10.0
• 8.0
• 6.0
• 4.0
• 2.0

0.0

• 20
• 18
• 16
• 14
• 12
• 10
• 8
• 6
• 4
• 2

I need to study charge sharing in other bias voltages, and the charge distribution Xcs [um] Xgenerated[um]

Conclusion

• We made the pixel sensor for ILC, SOFIST1 (my works: the pixel circuit and

the layout)

• I estimated the full depletion voltage, Vdep ~50V
• I checked cross talks (BPW14um)
• transistor <- sensor; BPW shuts this cross talk out,


and all transistors on the circuit layer works well.

• (sensor <- transistor; transistor affects the potential in the sensor)
• I need to study this effect to charge sharing and Psub<-Psub cross

talk

• Psub <- Psub ; negligible
• From these results of the simulations, SOFIST1 works well(BPW14um)
• I am making a table of charge sharing, and it will be the bench mark to
• measure. I’m also study charge sharing and distribution in other bias voltage.

24

Additional Slides

25

ILD & SiD

• ILC is going to be constructed for 2 experiments

• > ILD & SiD

26

VTX -> vertex detector

• TPC -> charged particle

tracker HCal -> E of hadrons ECal -> E of el and γ Muon -> Muon ID FCal ->Luminosity ILD

Beam Structure

27

• beam structure
• 1 train: 200ms(1ms for collisions, 199ms for rest)
• 1 bunch: ~337ns

Requirement to Sensor

28

• sensor size: 10mm x 125mm (max)
• spatial resolution: less than 3um
• low amounts of matters: (sensor thickness) < 100um
• pixel occupancy: less than 2%

AcVve$area$ 6250(H)×500(V) pixels$

• 125mm

10mm

8bit$ADC$×$6250ch$ (TBD)$Digital$memory$(SRAM?) Controller$ (Timing/Readout/Memory/Output) Data$transmission$interface Data$output$(parallel?)

• 20um

??mm

10mm 125mm

29

1 Pixel Layout

30

20u 20u

3x3 pixels layout

31

We ordered A-R-Tec to design the chip, SOFIST We’ve designed the pixel(my work), Ramp Generator, and column ADC

CSA’s Gain

• Sensor Cap : Csensor = 10f
• Feedback Cap : Cf = 5f
• Vout = (Csensor / Cf) * Vin
• CSA’s Gain ~ 2 (hopefully)

32

Csensor Cf RST_V Vin Vout

• 1MIP : ~4000e-
• Sensor Cap : 10f
• 1MIP : ~64mV

33

Vout[V]

• 1
• 0.75
• 0.5
• 0.25

0.25 0.5 0.75

Vin [V]

• 0.7
• 0.525
• 0.35
• 0.175

0.175 0.35 0.525 0.7

Vout [V]

• 0.6
• 0.45
• 0.3
• 0.15

0.15 0.3 0.45 0.6

Vin [V]

• 0.4
• 0.3
• 0.2
• 0.1

0.1 0.2 0.3 0.4

y = 1.8152x - 0.0005 R² = 0.9999

The gain linearity is conserved to 10MIP

• 25.0

• .5

RST_V Vin Vout Vin Vout

分割率

• X = Qr / (Ql + Qr) * d (d = 20u)

34

各Psubに収集された電荷量

Qback Ql Qc Qr X x0 4.00636E-16 4.38924E-18 4.09409E-16 4.38924E-18 2.12144E-01 x5 4.00685E-16 4.42831E-18 4.08315E-16 3.20338E-18 2.14579E-01 x6 4.00702E-16 5.65918E-19 4.04304E-16 3.03817E-18 2.79555E-02 x7 4.00733E-16 1.47268E-17 3.88854E-16 2.85009E-18 7.29807E-01 x8 4.00767E-16 4.38866E-17 3.59591E-16 2.7132E-18 2.17542E+00 x9 4.00794E-16 1.15959E-16 2.87381E-16 2.54875E-18 5.74994E+00 x10 4.00798E-16 1.99087E-16 2.0413E-16 2.42163E-18 9.87493086849017E+00 x20 4.00635E-16 4.065E-16 4.40007E-18 1.4677E-18 1.97858325991524E+01