Evaluation of SOFIST1 by TCAD simulation R.Tsuji (Yamanaka Lab.) - PowerPoint PPT Presentation

Evaluation of SOFIST1 by TCAD simulation R.Tsuji (Yamanaka Lab.) 2015/12/25th year-end workshop@Osaka Univ. 1

Contents • ILC Experiment • SOI Technology • The SOI Pixel Sensor, SOFIST1 • The Estimate of the Full Depletion Voltage • Cross Talk • backgate effect (circuit <- sensor) • sensor potential (sensor <- circuit) • Psub/Psub (one pixel <- one pixel) • (Charge Sharing) • Conclusion 2

ILC ILD detector SiD detector (on beamline) (parked) • I nternational L inear C ollider • linear electron-positron collider • 200 ~ 500 GeV in C.M. 
 (1 TeV in the future) e+ bunch compressor Damping Rings IR & detectors ILD garage e- source e+ source e- bunch positron 2 km compressor main linac 11 km central region 5 km total length ~31km electron main linac 11 km 2 km 3

One of ILC’s Purposes • ATLAS and CMS found the particle, “Higgs” • precise measurement of Higgs properties • LHC experiments has many backgrounds (pp collision) • electron-positron collider has less backgrounds We can measure the precise measurement at ILC Our group struggles to make a chip of the vertex detector for ILC 4

Requirement to Sensor • sensor size: 10mm x 125mm (max) • spatial resolution: less than 3um • low amounts of matters: (sensor thickness) < 100um • pixel occupancy: less than 2% � 125mm 125mm � 20um � 10mm � AcVve$area$ 10mm 6250(H) × 500(V) pixels $ � 8bit$ADC$×$6250ch$ � ??mm � (TBD)$Digital$memory$(SRAM?) � Controller$ Data$transmission$interface � (Timing/Readout/Memory/Output) � 5 Data$output$(parallel?) �

低下は大きな利点となる。 高速性 また、電源の限られている宇宙関係、人工衛星等に載せて行う実験では消費電力の 内層に冷却用のパイプ等の不要な物質を減らすことが出来る等の利点が挙げられる。 が導入される実験では電源系、冷却系の負担が減る。高エネルギー加速器実験では、 リーク電流が減少する。これにより、消費電力を抑えることが出来、大量に検出器 回路は絶縁膜によってシリコン基板部と回路部が絶縁されている為に 低消費電力 高速な読み出しが可能である。 領域の接合容量が絶縁膜によって大幅に低減する。寄生容量が減少することにより、 トランジスタよりも、ソース、ドレイン トランジスタは る。本節ではそれぞれの利点について詳細を述べる。 技術を半導体検出器に応用すると様々な利点が生まれ で述べたように、 の利点 型基板をセンサーとして使用する。 の断面図。下部の 図 SOI Technology • S ilicon O n I nsulator • sensor and ASIC in a chip • monolithic pixel detector • NO bonding 6

SOFIST1 • SO i for F ine measurement of S pace and T ime Ver.1 • this version is the prototype • 1pixel size : 20u x 20u Bias circuit • Column ADC readout 20um Row selector • Controlled by SEABAS Active area 50 × 50 pixels • without a discriminator 
 and circuits for time stamp • I worked on 
 8bit column ADC × 50ch the pixel architecture 
 Ramp Generator Output data Column selector and the layout (8bit) 7

大本・今村 試作チップの 大本・今村 ピクセル構成 案 Pixel Architecture Pre-amp Multi-buffer RST 5f 100f READ1 STORE1 PD READ2 STORE2 ピクセル回路への追加予定 • リセット電圧入力 • テスト信号入力 COL_OUT • referring to the circuit of XRPIX • I checked this circuit worked well, simulating it 8

TCAD Simulation in 2 Dimensions • Estimate of Full Depletion Voltage • Cross Talk • Backgate Effect (transistor <- Sensor) • Potential in the Sensor (transistor <- Sensor) • Psub/Psub (pixel <- pixel) • (Charge Sharing) 9

Sensor Basic Structure For TCAD Psub (P-type) Circuit layer 0.04um SiO 2 layer 0.2um Sensor layer BPW 50um N-type 10um 20um V bias 60um Y X 10

Estimate of Full Depletion Voltage(BPW14um) BPW14um Circuit layer(SiO 2 ) SiO 2 layer V=0 V=0 V=0 Sensor layer V bias Density of electrons VS Sensor depth(0 <= V bias <= 100) —> 11

Density of Electrons sofist1_2D_woMOS_wBPW14u_20151216#2_dis.dists0.Elec sofist1_2D_woMOS_wBPW14u_20151216#2_dis.dists10.Elec sofist1_2D_woMOS_wBPW14u_20151216#2_dis.dists40.Elec [ cm^ − 3 ] [ cm^ − 3 ] [ cm^ − 3 ] 9.50e+13 2.50e+12 2.50e+12 6.06e+11 2.08e+10 2.08e+10 3.86e+09 1.73e+08 1.73e+08 2.46e+07 1.44e+06 1.44e+06 1.57e+05 1.20e+04 1.20e+04 1.00e+03 1.00e+02 1.00e+02 V bias = 0V V bias = 5V V bias = 20V sofist1_2D_woMOS_wBPW14u_20151216#2_dis.dists120.Elec sofist1_2D_woMOS_wBPW14u_20151216#2_dis.dists80.Elec sofist1_2D_woMOS_wBPW14u_20151216#2_dis.dists160.Elec [ cm^ − 3 ] [ cm^ − 3 ] [ cm^ − 3 ] 2.50e+12 2.50e+12 2.50e+12 2.08e+10 2.08e+10 2.08e+10 1.73e+08 1.73e+08 1.73e+08 1.44e+06 1.44e+06 1.44e+06 1.20e+04 1.20e+04 1.20e+04 1.00e+02 1.00e+02 1.00e+02 V bias = 40V V bias = 60V V bias = 80V 12

e - density vs sensor depth Probe_Xm10_Ym0c0tom50c0.dat Probe_Xm0_Ym0c0tom50c0.dat Probe_X10_Ym0c0tom50c0.dat Psub 2 10 5 10 5 10 10 1 0 10 20 30 40 50 0 10 20 30 40 50 0 10 20 30 40 50 Probe_X20_Ym0c0tom50c0.dat Probe_X30_Ym0c0tom50c0.dat Probe_X40_Ym0c0tom50c0.dat Psub Psub 2 2 10 10 5 10 10 10 1 1 0 10 20 30 40 50 0 10 20 30 40 50 0 10 20 30 40 50 Probe_X50_Ym0c0tom50c0.dat Vbias = 50V Vbias = 20V Vbias = 30V Vbias = 60V 5 10 Vbias = 40V Vbias = 100V 0 10 20 30 40 50 V dep ~ 50V 13

Cross Talk(transistor <- sensor) V g =0V V s =0V (V d =1.5V) I d Circuit layer SiO 2 layer Sensor layer BPW14um V bias BPW exists to shut the cross talk(transistor <- sensor) I d vs V bias (w/ or w/o BPW) 14

GraphIV2 0.001 A w/ BPW 1e-4 0.0001 1e − 05 w/o BPW 1e − 06 1e − 07 Id [A] 1e − 08 IDrain 1e-9 1e − 09 1e − 10 1e − 11 1e − 12 1e-13 1e − 13 1e − 14 ::2D_NFZ50um_NIO_Tr_backgate_dtr10um_cur.Condition0 − VBack − IDrain ::2D_NFZ50um_NIO_Tr_backgate_dtr10um_BPW_cur.Condition0 − VBack − IDrain 1e − 15 − 10 0 10 20 30 40 50 60 70 80 90 100 110 0 100 VBack V V bias [V] BPW surely shuts backgate effect 15

How length can transistor protrude from the edge of BPW? • BPW 14um • I placed a transistor from away the BPW edge by 0u, ±0.5u, ±1.0u,,,,,, 16

GraphIV17 2.0e − 13 A 2.0e-13 − 2.0um − 1.5um − 0.5um Id [A] <— on the edge of BPW 0.0um 0.5um 1.0um 1.5e − 13 1.5um 2.0um <— on the center 3.0um between 2 Psubs 1.0e-13 IDrain 1.0e − 13 5.0e − 14 V bias [V] 0.0 0.0 − 10 0 10 20 30 40 50 60 70 80 90 100 110 0.0 50 VBack 100 V this value << ~4e-7A (the drain current @ operating point of the NMOS) 17

Potential in the Sensor at the Sensor/SiO2 interface Graph V bias = 50V 14 w/o BPW 12 Potential [V] BPW 14um 10 BPW 12um 8 BPW 16um 6 4 2 10 0 10 20 30 40 50 − X [um] 18

Charge Sharing(BPW14u) V 2 = 0.5V V 1 = 0.5V V 0 = 0.5V 14um (0,0) -4.5um + - 1980 pairs - + + - -49.5um V bias = 50V simulating, shifting by 1um 19

e - density [ cm^ − 3 ] [ cm^ − 3 ] [ cm^ − 3 ] 2.50e+12 2.00e+13 1.70e+13 sofist1_2D_woMOS_wBPW14u_charge_collection_TRAN_X0c0_dis.dists1.Elec sofist1_2D_woMOS_wBPW14u_charge_collection_TRAN_X0c0_dis.dists2.Elec sofist1_2D_woMOS_wBPW14u_charge_collection_TRAN_X0c0_dis.dists4.Elec 2.08e+10 1.74e+11 1.53e+11 1.73e+08 1.52e+09 1.37e+09 1.44e+06 1.32e+07 1.24e+07 1.20e+04 1.15e+05 1.11e+05 1.00e+02 1.00e+03 1.00e+03 t = 1e-12 t = 1e-11 t = 1e-10 [ cm^ − 3 ] [ cm^ − 3 ] 2.50e+12 2.50e+12 sofist1_2D_woMOS_wBPW14u_charge_collection_TRAN_X0c0_dis.dists6.Elec sofist1_2D_woMOS_wBPW14u_charge_collection_TRAN_X0c0_dis.dists8.Elec 2.08e+10 2.08e+10 1.73e+08 1.73e+08 1.44e+06 1.44e+06 Charge is generated 1.20e+04 1.20e+04 at X = 0.0 1.00e+02 1.00e+02 t = 1e-8 t = 1e-9 20

I vs TIME 3.e − 06 A IBack IPsub11 IPsub12 IPsub13 2.e − 06 1.e − 06 I [A] IBack 0. − 1.e − 06 1e-12 1e-10 Time [s] − 2.e − 06 − 1e − 15 1e − 14 1e − 13 1e − 12 1e − 11 1e − 10 1e − 09 1e − 08 1e − 07 1e − 06 1e-13 1e-11 1e-9 1e-8 1e-7 1e-6 TIME s 21