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EE-612: Lecture 22: CMOS Process Steps
Mark Lundstrom Electrical and Computer Engineering Purdue University West Lafayette, IN USA Fall 2006
www.nanohub.org
EE-612: Lecture 22: CMOS Process Steps Mark Lundstrom Electrical - - PowerPoint PPT Presentation
EE-612: Lecture 22: CMOS Process Steps Mark Lundstrom Electrical and Computer Engineering Purdue University West Lafayette, IN USA Fall 2006 NCN www.nanohub.org Lundstrom EE-612 F06 1 outline 1) Unit Process Operations 2) Process
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www.nanohub.org
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1) Oxidation 2) Diffusion 3) Ion Implantation 4) RTA/RTP 5) Chemical Vapor Deposition 6) Lithography 7) Etching 8) Metalization 9) Well Structures 10) Isolation 11) Source / Drain structures
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1) J.D. Plummer, M.D. Deal, P.B. Griffin, Silicon VLSI Technology, Fundamentals, Practice, and Modeling, Prentice Hall, Upper Saddle River, NJ, 2000. 2) S.A. Campbell, The Science and Engineering of Microelectronic Fabrication, 2nd Ed., Oxford Univ. Press, New York, 2001.
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fused quartz furnace tube
heater wafers
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phophorous m > 1
boron m < 1
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dopant-containing gas (e.g. POCl3)
Q = C x,t
∞
dx=2CS Dt π
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t = 0 ‘predep’
πDt
2
⎡ ⎣ ⎢ ⎤ ⎦ ⎥
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2 2ΔRp 2
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P r
e c t e d r a n g e ( μ m ) Acceleration energy (keV)
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tilted 3 deg
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lamps reflector quartz window wafer gas inlet
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wafer
gas inlet gas exhaust reaction chamber
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gas inlet gas exhaust heater wafer RF power in
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wavelength, λ shutter mask resist wafer
lens contact
proximity
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UV source lens 1 lens 2 wafer mask
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electric field at mask conventional mask phase shift mask intensity at wafer electric field at mask intensity at wafer
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resist:
when exposed to UV changes its solubility in specific chemicals wafer wafer wafer negative resist (less soluble after exposure) positive resist (more soluble after exposure)
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undercut wafer wet chemical etching (isotropic) dry etching (plasma or reactive ion etching - RIE) (anisotropic) wafer chemicals react with underlying material, but not resist ionized gases react with underlying material, but not resist
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mask lithography bias chrome resist
etch bias
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www.itrs.net 2005 Edition Tungsten (W) plugs for first layer metal dep CMP
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N+ N+ P (NA cm-3)
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(see Wong and Taur, IEDM, 1993, p. 705)
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(simulations from A. Asenov group,
35 nm MOSFET AFM measurements, Fujitsu
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From A. Asenov, Univ. of Glasgow
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For a basic, CMOS process flow for an STI (shallow trench isolation process), see: http://www.rit.edu/~lffeee/AdvCmos2003.pdf
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