EE-612: Lecture 25: CMOS Circuits: Part 2 Mark Lundstrom - - PowerPoint PPT Presentation

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EE-612: Lecture 25: CMOS Circuits: Part 2

Mark Lundstrom Electrical and Computer Engineering Purdue University West Lafayette, IN USA Fall 2006

www.nanohub.org

NCN

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Outline

1) Review 2) Speed (continued) 3) Power 4) Circuit performance

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CMOS inverter

VDD VIN VOUT PMOS NMOS

VDD VDD

V

• ->

OUT

VDD/2

VIN --> S B D S B D

transfer characteristic

VDD/2

noise margins

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importance of gain

Vout Vin VDD VDD VDD 2

Aυ = 1

must have gain to have noise margins

dVout dVin = Aυ = gmn + gmp

( ) r

• n || r
• p

( )> 1

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• utline

1) Review 2) Speed (continued) 3) Power 4) Circuit performance

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CMOS inverter speed

VDD VIN VOUT S D D S

+

• CTOT

Rswn = kn VDD IN (on) kn > 1 2 τ = 1 2 CTOTVDD 2IN (on) + CTOTVDD 2IP(on) ⎛ ⎝ ⎜ ⎞ ⎠ ⎟ τ = RswN + RswP

( )

2 CTOT τ = RswCTOT

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loaded propagation delay

VDD VIN

CTOT Cin Cout Cwire Cin Cin CTOT = Cout + CL + FO × Cin

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Miller C

VD

p-Si n+ n+

COV

+

• COV

VDD VDD

Vc(t << 0) = −VDD Vc(t >> 0) = +VDD ΔVc = 2VDD ΔQc = ΔVcCOV = 2VDDCOV = CMVDD CM = 2COV “feed forward”

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• n-current determines circuit speed

VDD VIN VOUT S D D S

+

• CTOT

1) quasi-static assumption 2) simplified ID - VDS

VDS VDSAT IN on

( )

IN

τ = RswCTOT Rsw ~ VDD / ID(ON)

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metrics for circuit speed

K.K. Ng, et al., “Effective On-Current of MOSFETs for Large-Signal Speed Consideration,” IEDM, Dec., 2001. M.H. Na, et al., “The Effective Drive Current in CMOS Inverters,” IEDM, Dec., 2002.

• J. Deng and H.S.P. Wong, “Metrics for Performance Benchmarking of

Nanoscale Si and Carbon Nanotube FETs Including Device Nonidealities,” IEEE Trans. Electron Dev., 53, pp. 1317-1366, 2006.

• R. Venugopal, et al., “Design of CMOS Transistors to Maximize Circuit

FOM Using a Coupled Process and Mixed Mode Simulation Methodology,” IEEE Electron Dev. Lett., 53, pp. 1317-1366, 2006.

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• utline

1) Review 2) Speed 3) Power 4) Circuit performance

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power

VDD VIN

+

• t

VDD Vin(t)

CTOT 1 2 CTOTVDD

2

T

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discharge cycle

+

• t

VDD Vin(t)

CTOT 1 2 CTOTVDD

2

T / 2

EC(0) = 1 2 CTOTVDD

2

EC(T / 2) = 0 P

dynamic = ΔE

T / 2 = CTOTVDD

2

T

Vin(t)

P

dynamic = α f CTOTVDD 2

switching activity

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discharge through a resistor

+

• t

VDD Vin(t)

CTOT Vc(t)

T / 2

VC(t) = Vc(0)e−t /RCTOT = VDD e−t /τ

Vin(t)

R +

• P

R(t) = VC 2(t) R

P

AVE =

P

R(t)dt T /2

∫

T / 2 = 2 T VDD

2

R

T /2

∫

e−2t /τdt = f CTOTVDD

2

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charging cycle

VDD VIN

+

• CTOT

1 2 CTOTVDD

2

does it take power to put energy in the capacitor?

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charging cycle (ii)

+

• t

VDD V(t)

CTOT Vc(t)

T / 2 V(t)

EC(T / 2) = 1 2 CTOTVDD

2

EC(0) = 0 EB = VDD

T /2

∫

i(t)dt EB = VDD i(t)

T /2

∫

dt = VDD Q EB = VDD Q = CTOTVDD

2

Ediss = 1 2 CTOTVDD

2

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charging cycle (iii)

+

• t

VDD V(t)

CTOT Vc(t)

T / 2 V(t)

R +

• Vc(t) = VDD − i t

( )R

i(t) = CTOT dVc dt i(t) = −RCTOT di dt i(t) = i(0+)e−t /τ = VDD R

( )e−t /τ

EB = VDD i(t)dt

T /2

∫

= CTOTVDD

2

Ediss = 1 2 CTOTVDD

2

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adiabatic charging

+

• t

VDD V(t)

CTOT Vc(t)

T V(t)

R +

• i(t) = CTOT

dV dt = CTOT VDD T P

R = i2R =

CTOTVDD T ⎛ ⎝ ⎜ ⎞ ⎠ ⎟

2

R Ediss = P

Rdt T

∫

= CTOT

2 VDD 2

T 2 RT Ediss = CTOTVDD

2

RCTOT T ⎛ ⎝ ⎜ ⎞ ⎠ ⎟

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• utline

1) Review 2) Speed 3) Power 4) Circuit performance 5) CMOS circuit metrics

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device impact on circuit performace

Question: Given a technology, how does circuit performance depend on transistor design (W, TOX, VDD, etc.) Taur and Ning assume a 250nm technology and explore this question by Spice simulation (see pp. 264 - 279). Can we understand the major trends simply?

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effect of transistor W on delay

τ = Rswn + Rswp

( )

2 CTOT = RswCTOT CTOT = Cout + Cwire + FO × Cin Rsw = kVDD ID(on) Cout ~ W Cin ~ W I(on) ~ W Rsw ~ 1/W

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loaded vs. unloaded delay

τ = RswCTOT = Rsw Cout + FO × Cin + Cwire

( )

i) unloaded: Cin and Cout dominate, CTOT ~ W

• -> τ independent of W

ii) loaded: CL dominates, CTOT ~ independent of W

• -> τ ~1/ W

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effect of TOX on delay

τ = RswCTOT = Rsw Cout + FO × Cin + CL

( )

i) intrinsic delay (CL = 0)

Rsw = kVDD / ID(ON) ~ TOX Cin ~ 1/ TOX Cout constant τ int ~ constant

ii) loaded delay (CL > 0)

τ loaded ≈ RswCL τ loaded ↑ as TOX ↑

(see Fig. 5.32 of Taur and Ning)

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effect of L on delay

τ = RswCTOT = Rsw Cout + FO × Cin + CL

( )

Rsw = kVDD / ID(ON) Cin ~ L Cout,CL constant τ ↑ as L ↑

(see Fig. 5.31 of Taur and Ning)

ID(ON) = W COXυ(0) VGS − VT

( )↓ as L ↑

Rsw ↑ as L ↑

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effect of VDD on delay

Rsw = kVDD / ID(ON) τ ~ 1 1− VT VDD ID(ON) = W COXυ(0) VGS − VT

( )

Rsw ~ VDD VDD − VT

( )

Rsw ~ 1 1− VT VDD

( )

τ = RswCTOT = Rsw Cout + FO × Cin + CL

( )

Cout = εSi WD ~ 1 VDD + Vbi

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delay vs. VDD

τ ~ 1 1− VT VDD

(see Fig. 5.33 of Taur and Ning)

VDD VT τ

fixed VT

VT VDD = 0.2 ID(off) ~ e−qVT /mkBT

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power-delay trade-off

τ ~ VDD VDD − VT

( )

f ~ 1− VT VDD

( )

P

static ~ ID(OFF)VDD ~ e−qVT /mkBTVDD

P

dynamic = α fCTOTVDD 2 ~ VDD 2

1− VT VDD

( )

circuit speed: dynamic (switching) power: static (leakage) power:

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power-delay trade-off

VDD VT P

dynamic ~ VDD 2

1− VT VDD

( )

(see Fig. 5.34 of Taur and Ning)

P

static ~ e−qVT /mkBTVDD

speed ~ 1− VT VDD

( )

increasing speed decreasing active power decreasing leakage power

HP LSP

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Outline

1) Review 2) Speed 3) Power 4) Circuit performance 5) CMOS circuit metrics

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key metrics

1) Switching energy: ES = 1 2 CVDD

2

2) Switching delay: τ S = CVDD ID(ON) 3) Dynamic power: P

D = α f CVDD 2

4) Energy-delay product: ESτ = 1 2 C 2VDD

3

ID(on)

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the energy-delay metric

Energy-delay product: ESτ = 1 2 C 2VDD

3

ID(on) ~ VDD

3

VDD − VT

( )

Minimum energy-delay product:

( )

1.5

S

• pt

DD T DD

E V V V τ ∂ = ⇒ = ∂

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device metrics for 65 nm technology node

1) Switching energy: ES = 1 2 CVDD

2 ≈ 21 aJ

2) Switching delay: τ S = CVDD ID(ON) = 0.64 ps 3) Dynamic power: P

D = α f CVDD 2

4) Energy-delay product: ESτ = 1 2 C 2VDD

3

ID(on) = 1.4 ×10−29 J-s

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circuit performance (high-speed logic)

Typical power dissipation of a logic chip: 100 W Dissipation of logic core: ≈ 20 W P

core = Ncore

CSVDD

2

2 fα = 107 × CS ×12 2 × 4 ×109

( )×10−1

Energy-delay product: ESτ ≈ 1.5 ×10−24 J-s ES ≈ CSVDD

2

2 CS ≈ 10 fF/node Average switching energy: = 6,000 aJ

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device circuit increase delay: switching energy: energy- delay:

from device to circuit

0.64 ps 250 ps ~ 400 × 21 aJ 6000 aJ ~300 × ~ 10−29 J-s ~ 10−24 J-s ~100,000 ×

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Outline

1) Review 2) Speed 3) Power 4) Circuit performance 5) CMOS circuit metrics

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conclusions / questions

1) Device metrics aren’t enough; the circuit is critical. 2) How close is CMOS to fundamental limits?