12/9/2014 Overview: Boundary Scan • Motivation ECE 553: TESTING AND • Bed-of-nails tester TESTABLE DESIGN OF • System view of boundary scan hardware • Elementary scan cell Elementary scan cell DIGITAL SYSTEMS DIGITAL SYSTEMS • Test Access Port (TAP) controller • Boundary scan instructions • Summary Boundary Scan 12/9/2014 2 Motivation for Standard Bed-of-Nails Tester Concept Bed-of-nails printed circuit board tester gone We put components on both sides of PCB & replaced DIPs with flat packs to reduce inductance Nails would hit components Reduced spacing between PCB wires Nails would short the wires PCB Tester must be replaced with built-in test delivery system -- JTAG does that Need standard System Test Port and Bus Integrate components from different vendors Test bus identical for various components One chip has test hardware for other chips 12/9/2014 3 12/9/2014 4 Bed-of-Nails Tester Purpose of Standard Lets test instructions and test data be serially fed into a component-under-test (CUT) Allows reading out of test results Allows RUNBIST command as an instruction Too many shifts to shift in external tests JTAG can operate at chip, PCB, & system levels Allows control of tri-state signals during testing Lets other chips collect responses from CUT Lets system interconnect be tested separately from components Lets components be tested separately from wires 12/9/2014 5 12/9/2014 6 1
12/9/2014 System Test Logic Instruction Register Loading with JTAG 12/9/2014 7 12/9/2014 8 System View of Interconnect Boundary Scan Chain View 12/9/2014 9 12/9/2014 10 Elementary Boundary Scan Cell Serial Board / MCM Scan 12/9/2014 11 12/9/2014 12 2
12/9/2014 Independent Path Board / MCM Parallel Board / MCM Scan Scan 12/9/2014 13 12/9/2014 14 Tap Controller Signals Tap Controller State Diagram Test Access Port (TAP) includes these signals: Test Clock Input ( TCK ) -- Clock for test logic Can run at different rate from system clock Test Mode Select ( TMS ) -- Sw itches system from functional to test mode Test Data Input ( TDI ) Test Data Input ( TDI ) -- Accepts serial test Accepts serial test data and instructions -- used to shift in vectors or one of many test instructions Test Data Output ( TDO ) -- Serially shifts out test results captured in boundary scan chain (or device ID or other internal registers) Test Reset ( TRST ) -- Optional asynchronous TAP controller reset 12/9/2014 15 12/9/2014 16 TAP Controller Power-Up Reset Tap Controller Timing Logic 12/9/2014 17 12/9/2014 18 3
12/9/2014 SAMPLE / PRELOAD Instruction -- SAMPLE Purpose: 1. Get snapshot of normal chip output signals 2. Put data on bound. scan chain before next instr. Boundary Scan Instructions Boundary Scan Instructions Boundary Scan Instructions Boundary Scan Instructions 12/9/2014 20 SAMPLE / PRELOAD Instruction -- EXTEST Instruction PRELOAD Purpose: Test off-chip circuits and board- level interconnections 12/9/2014 21 12/9/2014 22 INTEST Instruction INTEST Instruction Clocks Purpose: 1. Shifts external test patterns onto component Control of applied system clock during INTEST 2. External tester shifts component responses out Use of TCK for on-chip system logic clock 12/9/2014 23 12/9/2014 24 4
12/9/2014 RUNBIST Instruction CLAMP Instruction Purpose: Allow s you to issue BIST command to component through JTAG hardw are Purpose: Forces component output signals Optional instruction to be driven by boundary-scan register Bypasses the boundary scan chain by Lets test logic control state of output pins using the one-bit Bypass Register 1. Can be determined by pin boundary scan cell y p y Optional instruction 2. Can be forced into high impedance state May have to add RESET hardw are to BIST result (success or failure) can be left in control on-chip logic so that it does not boundary scan cell or internal cell get damaged (by shorting 0’s and 1’s onto Shift out through boundary scan chain an internal bus, etc.) May leave chip pins in an indeterminate state (reset required before normal operation resumes) 12/9/2014 25 12/9/2014 26 Device ID Register --JEDEC IDCODE Instruction Code Purpose: Connects the component device identification register serially betw een TDI MSB LSB and TDO In the Shift-DR TAP controller state I 27 12 27 12 11 1 11 1 0 0 th Shift DR TAP t ll t t 31 28 Part Manufacturer ‘1’ Allow s board-level test controller or Version Number Identity external tester to read out component ID (4 bits) (16 bits) (11 bits) (1 bit) Required w henever a JEDEC identification register is included in the design 12/9/2014 27 12/9/2014 28 USERCODE Instruction HIGHZ Instruction • Purpose: Intended for user-programmable components (FPGA’s, EEPROMs, etc.) Purpose: Puts all component output pin signals into high-impedance state – Allows external tester to determine user programming of component Control chip logic to avoid damage in this mode May have to reset component after HIGHZ runs • Selects the device identification register as serially connected between TDI and TDO connected between TDI and TDO Optional instruction p • User-programmable ID code loaded into device identification register – On rising TCK edge • Switches component test hardware to its system function • Required when Device ID register included on user- programmable component 12/9/2014 29 12/9/2014 30 5
12/9/2014 BYPASS Instruction Optional / Required Instructions Purpose: Bypasses scan chain w ith 1-bit register Instruction Status BYPASS Mandatory CLAMP Optional EXTEST EXTEST Mandatory Mandatory HIGHZ Optional IDCODE Optional INTEST Optional RUNBIST Optional SAMPLE / PRELOAD Mandatory USERCODE Optional 12/9/2014 31 12/9/2014 32 Summary Boundary Scan Standard has become absolutely essential -- No longer possible to test printed circuit boards w ith bed-of-nails tester Not possible to test multi-chip modules at all w ithout it Supports BIST, external testing w ith Automatic Test Equipment, and boundary scan chain reconfiguration as BIST pattern generator and response compacter Now getting w idespread usage 12/9/2014 33 6
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