9/25/2014 Overview • Structural vs. functional test • Definitions ECE 553: TESTING AND • Completeness TESTABLE DESIGN OF • Conditions for finding a test • Algebras • Algebras DIGITAL SYSTES DIGITAL SYSTES • Types of Algorithms – classical • Complexity • Summary • Appendices Combinational ATPG Basics 9/25/2014 2 Carry Circuit Functional vs. Structural ATPG Functional vs. Structural ATPG 9/25/2014 3 9/25/2014 4 Definition of Automatic Test- Functional vs. Structural (Contd.) Functional vs. Structural (Contd.) Pattern Generator • Functional ATPG – generate complete set of tests for circuit input-output combinations • Operations on digital hardware: – 129 inputs, 65 outputs: – Inject fault into circuit modeled in computer – 2 129 = 680,564,733,841,876,926,926,749, – Use various ways to activate and propagate fault effect through hardware to circuit output 214,863,536,422,912 patterns – Output flips from expected to faulty signal – Using 1 GHz ATE, would take 2.15 x 10 22 years • Electron-beam ( E-beam ) test observes internal signals El t b ( E b ) t t b i t l i l • Structural test: St t l t t – No redundant adder hardware, 64 bit slices – “picture” of nodes charged to 0 and 1 in different colors – Each with 27 faults (using fault equivalence) – Too expensive – At most 64 x 27 = 1728 faults (tests) • Scan design – add test hardware to all flip-flops to – Takes 0.000001728 s on 1 GHz ATE make them a shift register in test mode • Designer gives small set of functional tests – augment with – Can shift state in, scan state out structural tests to boost coverage to 98 + % – Widely used – makes sequential test combinational – Costs: 5 to 20% chip area, circuit delay, extra pin, longer test sequence 9/25/2014 5 9/25/2014 6 1
9/25/2014 Notation Notation Algorithm Completeness Failing Good • Definition: Algorithm is c omplete if it Symbol Meaning Circuit Circuit ultimately can search entire binary (decision) 1/0 0 D 1 space, as needed, to generate a test 0/1 1 D 0 Roth’s • Untestable fault or Undetectable fault • Untestable fault or Undetectable fault – no test no test 0/0 0/0 0 0 0 0 0 0 Algebra 1 1/1 for it even after entire space is searched 1 1 X X/X X X • Combinational circuits only – untestable X 0/X 0 G0 faults are redundant, showing the presence of 1/X X 1 G1 Muth’s unnecessary hardware X/0 0 X Additions F0 X/1 1 X F1 9/25/2014 7 9/25/2014 8 Roth’s and Muth’s Higher-Order Roth’s and Muth’s Higher-Order Conditions for Finding a Test Algebras Algebras • Fault excitation – the signal value at the fault • Represent two machines, which are simulated site must be different from the value of the simultaneously by a computer program: stuck-at fault (thus fault site must contain a D or – Good circuit machine (1 st value) a D) – Bad circuit machine (2 nd value) • The fault effect must be propagated to a The fault effect must be propagated to a • Better to represent both in the algebra: primary output (A D or a D must appear at the – Need only 1 pass of ATPG to solve both output) – Good machine values that preclude bad machine values • Some simple observations become obvious sooner & vice versa – There must be at least a D or a D on some circuit • Needed for complete ATPG: nets) – Combinational: Multi-path sensitization, Roth Algebra – D’s must form a chain to some output – Sequential: Muth Algebra -- good and bad machines may have different initial values due to fault 9/25/2014 9 9/25/2014 10 Random-Pattern Generation Random-Pattern Generation Exhaustive Algorithm • Flow chart for • For n -input circuit, generate all 2 n input method patterns • Use to get tests • Infeasible, unless circuit is partitioned into for 60-80% of cones of logic, with f l i ith ≤ ≤ 15 i 15 inputs t faults, then – Perform exhaustive ATPG for each cone switch to D- – Misses faults that require specific activation algorithm or patterns for multiple cones to be tested other ATPG for rest 9/25/2014 11 9/25/2014 12 2
9/25/2014 Boolean Difference (Sellers, Hsiao, Boolean Difference (Sellers, Hsiao, Boolean Difference Symbolic Method Boolean Difference Symbolic Method Bearnson) Bearnson) (Sellers et al .) (Sellers et al .) • Shannon’s Expansion Theorem: • F ( X 1 , X 2 , …, X n ) = X 2 F ( X 1 , 1, …, X n ) + X 2 F ( X 1 , 0, …, X n ) • • Boolean Difference (partial derivative): ∂ ∂ F j ⊕ = Fj (1, X1 , X2 , …, Xn ) Fj (0, X1 , …, Xn ) ∂ g g = G ( X 1 , X 2 , …, X n ) for the fault site • Fault Detection Requirements for g stuck-at 0: f j = F j ( g , X 1 , X 2 , …, X n ) G ( X 1 , X 2 , …, X n ) = 1 ≤ ≤ 1 j m ∂ F j ⊕ = Fj (1, X1 , X2 , …, Xn ) Fj (0, X1 , …, Xn ) = 1 ≤ X i = 0 or 1 for 1 i n ≤ ∂ g 9/25/2014 13 9/25/2014 14 Path Sensitization Method - Example Path Sensitization Method - Example Path Sensitization Method -Example Path Sensitization Method -Example 1 Fault Sensitization Try path f – h – k – L. This path is blocked at j , 2 Fault Propagation since there is no way to justify the 1 on i 3 Line Justification 1 D D D D 1 D 0 1 1 9/25/2014 15 9/25/2014 16 Path Sensitization Method Path Sensitization Method Path Sensitization Method Circuit Path Sensitization Method Circuit Try simultaneous paths f – h – k – L and Example Example g – i – j – k – L. These paths blocked at k because Final try: path g – i – j – k – L – test found! D-frontier (chain of D or D ) disappears 1 D 0 D 0 D 1 1 D 1 D D D D D D 1 1 1 9/25/2014 17 9/25/2014 18 3
9/25/2014 Summary Computational Complexity • Basic definitions explained • Ibarra and Sahni analysis – NP-Complete • Developed notation and required algebra that (no polynomial expression found for compute time, will be used for test generation and fault presumed to be exponential) simulation • Worst case: W • Basics of test generation developed no_pi inputs, 2 no_pi input combinations no_ff flip-flops, 4 no_ff initial flip-flop states • Complexity of test generation addressed × (good machine 0 or 1 bad machine 0 or 1) • Appendix contains historical reference to the work to forward or reverse simulate n logic stuck-at fault model, an example of BDD, an gates α n instantiation of SAT problem. • Complexity: O ( n x 2 no_pi x 4 no_ff ) 9/25/2014 19 9/25/2014 20 Origins of Stuck-Faults • Eldred (1959) – First use of structural testing Appendices for the Honeywell Datamatic 1000 computer • Galey, Norby, Roth (1961) – First publication of stuck at 0 and stuck at 1 faults of stuck-at-0 and stuck-at-1 faults • Seshu & Freeman (1962) – Use of stuck-faults for parallel fault simulation • Poage (1963) – Theoretical analysis of stuck-at faults 9/25/2014 21 9/25/2014 22 Circuit and Binary Decision Tree Circuit and Binary Decision Tree Binary Decision Diagram Binary Decision Diagram • BDD – Follow path from source to sink node – product of literals along path gives Boolean value at sink • Rightmost path: A B C = 1 • Problem: Size varies greatly P bl Si i l with variable order 9/25/2014 23 9/25/2014 24 4
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