Boundary Scan Test of Belle II Pixel Detector Electronics Seeon - - PowerPoint PPT Presentation

▶
boundary scan test of belle ii pixel detector electronics
SMART_READER_LITE
LIVE PREVIEW

Boundary Scan Test of Belle II Pixel Detector Electronics Seeon - - PowerPoint PPT Presentation

Jan 13, 2024 168 likes •521 views

Boundary Scan Test of Belle II Pixel Detector Electronics Seeon 12.05.2015 19 th International Workshop on DEPFET Detectors and Applications Philipp Leitl PXD bump bonds ASIC Pins Switcher 96 DCD 431 DHPT 255 } 6x Switcher 4x

slide-1
SLIDE 1

Boundary Scan Test of Belle II Pixel Detector Electronics

Seeon 12.05.2015 19th International Workshop on DEPFET Detectors and Applications Philipp Leitl

slide-2
SLIDE 2

12/05/15 2

Leitl

PXD bump bonds

  • 6x Switcher
  • 4x DCD
  • 4x DHPT

ASIC Pins Switcher 96 DCD 431 DHPT 255

}

3320 for each half ladder

→ 132.800 bump bonded ASIC pins

slide-3
SLIDE 3

12/05/15 3

Leitl

PXD bump bonds

X-ray inspection photograph of DCD chip bump pitch: 200µm in x and 180µm in y not accessible for a probe station with needles

slide-4
SLIDE 4

12/05/15 4

Leitl

JTAG

IEEE Std. 1149.1 Joint Test Action Group (JTAG) additional boundary-scan cells at the I/Os of an IC four additional I/O ports Test Access Port (TAP) TCK test clock TMS test mode select TDI test data input TDO test data output (TRST test reset)

slide-5
SLIDE 5

12/05/15 5

Leitl

TAP controller

State transition diagram of the TAP controller (Test Access Port) 16 state machine controlled by TCK and TMS

slide-6
SLIDE 6

12/05/15 6

Leitl

JTAG

IEEE Std. 1149.1 Joint Test Action Group (JTAG) additional boundary-scan cells at the I/Os of an IC four additional I/O ports Test Access Port (TAP) TCK test clock TMS test mode select TDI test data input TDO test data output (TRST test reset) Daisy Chain

slide-7
SLIDE 7

12/05/15 7

Leitl

Boundary Register Cell

two multiplexer two flip-flops

slide-8
SLIDE 8

12/05/15 8

Leitl

Chain of Boundary Scan ICs

slide-9
SLIDE 9

12/05/15 9

Leitl

Interconnect Test

slide-10
SLIDE 10

12/05/15 10

Leitl

PXD bump bonds

ASIC Pins BSC (Pins) Switcher 96 10 DCD 431 80 DHPT 255 97

  • 132.800 bump bonded ASIC pins
  • 30.720 accessible through BS

→ ~ 23% direct test coverage

(additional functional tests: power pins, JTAG pins, CLK, ...)

slide-11
SLIDE 11

12/05/15 11

Leitl

ID Code

hex binary Switcher18v2 23456789 0010 0011010001010110 01111000100 1 DCD 12345678 0001 0010001101000101 01100111100 0 DHPT1.0 44485011 0100 0100010010000101 00000001000 1

slide-12
SLIDE 12

12/05/15 12

Leitl

ID Code

hex binary Switcher18v2 23456789 0010 0011010001010110 01111000100 1 DCD 12345678 0001 0010001101000101 01100111100 0 DHPT1.0 44485011 0100 0100010010000101 00000001000 1

slide-13
SLIDE 13

HARDWARE

slide-14
SLIDE 14

12/05/15 14

Leitl

JTAG Breakout Board

slide-15
SLIDE 15

12/05/15 15

Leitl

JTAG Breakout Board

slide-16
SLIDE 16

12/05/15 16

Leitl

JTAG Breakout Board

slide-17
SLIDE 17

12/05/15 17

Leitl

JTAG Breakout Board

slide-18
SLIDE 18

12/05/15 18

Leitl

JTAG Breakout Board

slide-19
SLIDE 19

12/05/15 19

Leitl

JTAG Breakout Board

slide-20
SLIDE 20

12/05/15 20

Leitl

JTAG Breakout Board

slide-21
SLIDE 21

12/05/15 21

Leitl

JTAG Breakout Board

slide-22
SLIDE 22

SOFTWARE

slide-23
SLIDE 23

12/05/15 23

Leitl

Boundary Scan Software

  • New commercial system needed offers from different vendors

→

  • demo-version in the meantime
  • different JTAG controller adapter needed

→

  • Requirement: Boundary Scan Description Language (BSDL) files
  • DHP and DHPT:

software generated

  • SwitcherB18 v1 and v2: manually written by Christian Kreidl
  • DCD:

manually written by me

slide-24
SLIDE 24

12/05/15 24

Leitl

BSDL File DCD

Verilog file (jtag.v): BSDL file:

80 BSCs (8 columns with 8x DO and 2x DI each)

+ 4 additional BSCs 84 BSC in total BS_input_cell_sync_reset_I BS_input_cell_clk_I BS_output_cell_return_clk BS_input_cell_test_injection_en_I

slide-25
SLIDE 25

12/05/15 25

Leitl

First Boundary Scan Tests

slide-26
SLIDE 26

12/05/15 26

Leitl

EMCM P6-1

  • ld ASICs: 1x DHP0.2, 1x DCD and 1x SwitcherB18v1
slide-27
SLIDE 27

12/05/15 27

Leitl

EMCM P6-1

TRG_P

  • ld ASICs: 1x DHP0.2, 1x DCD and 1x SwitcherB18v1
slide-28
SLIDE 28

12/05/15 28

Leitl

EMCM P4-1

  • ld ASICs: 4x DHP0.2, 4x DCD and 6x SwitcherB18v1

(JTAG chain through Switchers not working)

slide-29
SLIDE 29

12/05/15 29

Leitl

EMCM P4-1

Toggle TRG signal

slide-30
SLIDE 30

12/05/15 30

Leitl

EMCM P4-1

clicking

Interconnect test between DHP: DO0(0) and DCD: DI0(0)

slide-31
SLIDE 31

12/05/15 31

Leitl

EMCM W17-3

change in connectors (Infiniband RJ45) → changes in the BSDL files (not for the DCD) change in the TRG signal (not static any more) change in maximal speed (≤ 3 MHz, best 1 MHz) new DHE new ASICs

slide-32
SLIDE 32

12/05/15 32

Leitl

EMCM ProveCard

slide-33
SLIDE 33

12/05/15 33

Leitl

EMCM ProveCard

slide-34
SLIDE 34

12/05/15 34

Leitl

Summary and Outlook

  • Overview of Boundary Scan method
  • Introduction of JTAG Breakout Board (JBB)

successfully tested and assembly finished

  • System of hardware (incl. probe station) and software

(incl. BSDL files) working

  • Getting familiar with the chosen JTAG software
  • Development of a standardized procedure for testing

the new PXD9 modules