Outline Bed-of-nails tester Motivation for boundary scan standard - - PowerPoint PPT Presentation

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IEEE 1149.1 JTAG

Boundary Scan Standard

Shaahin Hessabi Department of Computer Engineering Sharif University of Technology Adapted, with modifications, from lecture notes prepared by the book authors

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Outline

 Bed-of-nails tester  Motivation for boundary scan standard  System view of boundary scan hardware  Elementary scan cell  Test Access Port (TAP) controller  Boundary scan instructions  Summary

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Bed-of-Nails Tester Concept

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Bed-of-Nails Tester

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Motivation for Standard

 Bed-of-nails printed circuit board tester gone

• We put components on both sides of PCB &

replaced DIPs with flat packs to reduce inductance

 Nails would hit components

• Reduced spacing between PCB wires

 Nails would short the wires

• PCB Tester must be replaced with built-in test

delivery system -- JTAG does that

• Need standard System Test Port and Bus
• Integrate components from different vendors

 One chip has test hardware for other chips  Test bus identical for various components

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Purpose of Standard

 Lets test instructions and test data be serially fed into a CUT

• Allows reading out test results
• Allows RUNBIST command as an instruction

 Too many shifts to shift in external tests

 JTAG can operate at chip, PCB, & system levels  Allows control of tri-state signals during testing  Lets other chips collect responses from CUT  Lets system interconnect be tested separately from components  Lets components be tested separately from wires

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System Test Logic

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Instruction Register Loading with JTAG

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System View of Interconnect

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Boundary Scan Chain View

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Elementary Boundary Scan Cell

2.

Scan mode: Shift DR = 1

First scan FF is driven by TDI, Last scan FF drives TDO 3.

Capture mode: Shift DR = 0

4.

Update mode: Mode-control = 1

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1.

Normal mode: Mode-control = 0

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Serial Board / MCM Scan

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Parallel Board / MCM Scan

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Independent Path Board / MCM Scan

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Tap Controller Signals

 Test Access Port (TAP) includes these signals:

• Test Clock Input (TCK) -- Clock for test logic

 Can run at different rate from system clock

• Test Mode Select (TMS) -- Switches system from

functional to test mode

• Test Data Input (TDI) -- Accepts serial test data

and instructions -- used to shift in vectors or one

• f many test instructions
• Test Data Output (TDO) -- Serially shifts out test

results captured in boundary scan chain (or device ID or other internal registers)

• Test Reset (TRST) -- Optional asynchronous TAP

controller reset

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Tap Controller State Diagram

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States of TAP Controller

 Test-Logic-Reset: normal mode  Run-Test/Idle: wait for internal test such as BIST  Select-DR-Scan: initiate a data-scan sequence  Capture-DR: load test data in parallel  Shift-DR: load test data in series  Exit1-DR: finish phase-1 shifting of data  Pause-DR: temporarily hold the scan operation (e.g., allow the

bus master to reload data)

 Exit2-DR: finish phase-2 shifting of data  Update-DR: parallel load from associated shift registers

Note: Controls for IR are similar to those for DR.

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Tap Controller Timing

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TAP Controller Power-Up Reset Logic

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Boundary Scan Instructions

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Major Modes of Operation

 Non-invasive mode: standard provides resources guaranteed to

be independent of system logic

• These resources enable asynchronous communication with the outside

world (serially read in test data and instructions or serially read out test results)

• Activities are invisible to the normal IC behavior

 Pin-permission modes: takes control of the IC I/O pins, thus

disconnecting the system logic from the outside world.

• Allow testing of the system interconnect separately from component

testing, and also allow testing of components separately from system interconnect testing.

• The testing activities totally disrupt the normal IC behavior.

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SAMPLE / PRELOAD Instruction-- SAMPLE

Purpose:

1.

Get snapshot of normal chip output signals

2.

Put data on boundary scan chain before next instruction

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SAMPLE / PRELOAD Instruction -- PRELOAD

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EXTEST Instruction

 Purpose: Test off-chip circuits and board-level interconnections

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Execution of EXTEST Instruction

Phase 1: Shift-DR (Chip1)

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Phase 2: Update-DR (Chip1) Capture-DR (Chip2) Phase 3: Shift-DR (Chip2)

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Execution of INTEST Instruction

Phase 1: Shift-DR

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Phase 2: Update-DR Purpose: 1. Shifts external test patterns onto component

• 2. External tester shifts component responses out

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Execution of INTEST Instruction (cont’d)

Phase 3: Capture-DR

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Phase 4: Shift-DR

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RUNBIST Instruction

 Purpose: Allows you to issue BIST command to component through JTAG hardware  Optional instruction  Lets test logic control state of output pins 1. Can be determined by pin boundary scan cell

• 2. Can be forced into high impedance state

 BIST result (success or failure) can be left in boundary scan cell or internal cell

• Shift out through boundary scan chain

 May leave chip pins in an indeterminate state (reset required before normal operation resumes)

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CLAMP Instruction

 Purpose: Forces component output signals to be driven by

boundary-scan register

 Bypasses the boundary scan chain by using the one-bit

Bypass Register

 Optional instruction  May have to add RESET hardware to control on-chip logic

so that it does not get damaged (by shorting 0’s and 1’s onto an internal bus, etc.)

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IDCODE Instruction

 Purpose: Connects the component device identification register serially between TDI and TDO

• In the Shift-DR TAP controller state

 Allows board-level test controller or external tester to read out component ID  Required whenever a JEDEC identification register is included in the design

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Device ID Register --JEDEC Code

27 12 Part Number (16 bits) 11 1 Manufacturer Identity (11 bits) ‘1’ (1 bit)

31 28 Version (4 bits)

MSB LSB

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USERCODE Instruction

 Purpose: Intended for user-programmable components

(FPGA’s, EEPROMs, etc.)

• Allows external tester to determine user programming of component

 Selects the device identification register as serially connected between

TDI and TDO

 User-programmable ID code loaded into device identification register

• On rising TCK edge

 Required when Device ID register included on user-programmable

component

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HIGHZ Instruction

 Purpose: Puts all component output pin signals into high-

impedance state

 Control chip logic to avoid damage in this mode  May have to reset component after HIGHZ runs  Optional instruction

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BYPASS Instruction

 Purpose: Bypasses scan chain with 1-bit register

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Optional / Required Instructions

Instruction BYPASS CLAMP EXTEST HIGHZ IDCODE INTEST RUNBIST SAMPLE / PRELOAD USERCODE Status Mandatory Optional Mandatory Optional Optional Optional Optional Mandatory Optional

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Summary

 Boundary Scan Standard has become absolutely essential;

• No longer possible to test printed circuit boards with

bed-of-nails tester

• Not possible to test multi-chip modules at all without it
• Supports BIST, external testing with ATE, and

boundary scan chain reconfiguration as BIST pattern generator and response compacter

• Now getting widespread usage
• Use scanedu for practicing with JTAG concepts