SLIDE 28 DATA IN Sampling Clock 2.15MHz CLK 43MHz LVDS OUT LVDS IN INPUT DATA CONTROL Circular Buffer & RAM 256 x 16 bit CONTROL LOGIC FRAME BUILDER DATA OUT CONTROL IN FPGA
Structure and functions of FINESSE board for ECL Barrel/CsI(Tl)
- The FINESSE board receives data from one SHAPER&ADC Barrel
module (16 channels), or 64 channels per one CoPPER module.
- The FINESSE board transfer to ShaperADC Barrel module
43MHz data transfer Clock and 2.15MHz sampling Clock.
- Input Data Flow -->20 15-bit words (16 words data + 4 words status)
per Sampling Clock period (~500ns), or 43*10^6 words/sec.
- Data are continuously recorded to a circular buffer (256 16 bit words
~ 20 words x 12 samples ~ 6μs).
- Under control of L1 trigger signal the predefined amount of samples
for each channel are transfer to FIFO CoPPER module. L1 TRIGGER
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T.Tsukamoto@2ndSuperBWS2004/04/23
