Calorimeter Electronics/Pileus and Endcap Calorimeter Upgrade at - PowerPoint PPT Presentation

Calorimeter Electronics/Pileus and Endcap Calorimeter Upgrade at Belle T. Tsukamoto for Belle-ECL group @ 2 nd SuperB WS 2004/04/23 ● Belle Calorimenter(ECL) – Configuration – Readout eletronics ● Present status and BG estimation – Fake hits – Pileup ● Upgrade plan for Super-(KEK)B – Endcap : pure CsI – Barrel : readout 1 T.Tsukamoto@2ndSuperBWS2004/04/23

● Belle Calorimenter(ECL) – Configuration ● Counter : CsI(Tl)(30cm) + 2 PD's + preamp ● Barrel(6624)/FWD(1152)/BWD(960) 2 T.Tsukamoto@2ndSuperBWS2004/04/23

– Readout electronics ● Peak Hold ADC: Event trigger => gate => QT with TDC 3 T.Tsukamoto@2ndSuperBWS2004/04/23

● Present status and BG estimation – Recorded data in random trigger events (Ehit>0.5MeV) Sparsification threshold ● Energy distibution of BG clusters Barrel only Total 4 T.Tsukamoto@2ndSuperBWS2004/04/23

● Number of BG clusters with energy > E Total Barrel only 5 T.Tsukamoto@2ndSuperBWS2004/04/23

● Angular distribution of BG clusters Hits/Event FW D BWD E>20MeV Barrle E>50MeV 6 T.Tsukamoto@2ndSuperBWS2004/04/23

– Pileup noise ● Local run data are taken without sparsification ● Width of pedestals show effects of pileup noise Additional fluctuation Signal pulse (on-time signal) BG signals (off-timing signals) 7 T.Tsukamoto@2ndSuperBWS2004/04/23

– Width of pedestals vs. Theta position Barrle FWD BWD With beams Without beams 8 T.Tsukamoto@2ndSuperBWS2004/04/23

– BG estimation ● model/parameterization to explain pedestal widening ===> current and vaccuum pressure explained data well Vac. pressure Average photon Beam energy Average Sensitive current BG rate time 9 T.Tsukamoto@2ndSuperBWS2004/04/23

● Upgrade plan for Super-(KEK)B – To reduce fake hits ● Use timing information ==> waveform sampling – To reduce pileup noise ● Reduce sensitive time ● Endcaps : more BG ==> pure CsI ● Barrel : CsI(Tl) with shorter shaping time (1 µ s-->0.5 µ s) 10 T.Tsukamoto@2ndSuperBWS2004/04/23

● BG estimation and planned upgrade ECL(1) Dependence of pileup noise (pedestal width) vs. Background BG at L=10 34 cm -2 s -1 is 1(normalized) Pure CsI 30ns shaping Red :current Belle CsI(Tl) Blue:planned scheme (Black:recent data) Pure CsI 30ns shaping CsI(Tl) 0.5 µ s shaping 11 T.Tsukamoto@2ndSuperBWS2004/04/23

● BG estimation and planned upgrade ECL(2) FWD Energy resolution E γ 100MeV 200MeV 500MeV Present CsI(Tl) CsI(Tl) with τ =0.5 µ s Pure CsI with τ = 30ns BWD Barrel 12 T.Tsukamoto@2ndSuperBWS2004/04/23

● Radiation dose – Radiation dose measured by present ECL – Dose <==> int. of output <==> Int. of PD bias current Dose (rad/crystal) Time 13 T.Tsukamoto@2ndSuperBWS2004/04/23 (day)

– CsI(Tl) : results before installation K. Kazui et. al, Nucl. Instr. Meth. A394(1997)46-56, NWU-HEP 96-03,TIT-HPE 96-11 Endcap Barrel x20 BG operation Barrel Endcap Present operation T.Tsukamoto@2ndSuperBWS2004/04/23 14

● R & D status of Endcap : pure CsI – Beam test at BINP – 5 x 4 = 20 counters for a part of FWS Endcap 15 T.Tsukamoto@2ndSuperBWS2004/04/23

– Radiation hardness test with pure CsI Relative light output x20 BG @ Endcap Dose(rad) 16 T.Tsukamoto@2ndSuperBWS2004/04/23

● Beam test at BINP ● Pure CsI counter with PMT Same wrapping as the present Belle CsI(Tl) counter modified preamp PMT Hamamatsu R2185UV 17 T.Tsukamoto@2ndSuperBWS2004/04/23

– Light output test with Cs 137 18 T.Tsukamoto@2ndSuperBWS2004/04/23

● PMT Hamamatsu R2185UV ● Cin ~10pF B q PMT 30% gain under 1.5T mag. field 1.5T Endcap PMT gain and its behavior in magnetic field 19 T.Tsukamoto@2ndSuperBWS2004/04/23

● Electronics for pure CsI + PMT ● Prototype for waveform sampling 20 T.Tsukamoto@2ndSuperBWS2004/04/23

● Test beam line and CsI counter setup 21 T.Tsukamoto@2ndSuperBWS2004/04/23

● Cosmic ray test (1) ● Average light output av.~10,000p.e./MeV Light output measurement by cosmic ray 22 T.Tsukamoto@2ndSuperBWS2004/04/23

● Cosmic ray test (2) ● uniformity of light output 23 T.Tsukamoto@2ndSuperBWS2004/04/23

● Energy resolution (Compton edge) Pure CsI counters(this beam test) MC expectation CsI(Tl) (beam test) 24 T.Tsukamoto@2ndSuperBWS2004/04/23

● Time resolution by pure CsI counter Eg=100MeV Better than 1ns --> st=20ns can be expeced for CsI(Tl) 25 T.Tsukamoto@2ndSuperBWS2004/04/23

● R & D status : readout electronics – Waveform sampling TKO module (detector side) – COPPER + FINESSE will handle digitized signal In Electronics Inside At the detector Hut NOW the Detector TKO Barrel Barrel x16 x6 FUSTBUS Shaper 1μs + TDC QT Crystal CsI(Tl) 96 Endcup Endcup 3 range x 12 bit 2PD + 2Preamp ch/module 16 ch/module TKO VME x16 Crystal CsI(Tl) x4 Barrel Barrel Shaper 0.5μs + CoPPER 2PD + 2Preamp ADC 64 ch/module 2 range x 14 bit Upgrade 16 ch/module TKO VME x4 x16 Crystal pure CsI Endcup Endcup Shaper 30ns + CoPPER PT + Preamp ADC 64 ch/module 2 range x 14 bit Upgrade 16 ch/module 26 T.Tsukamoto@2ndSuperBWS2004/04/23

Waveform sampling module for BARREL CsI(Tl) - 16 Channels on TKO board. - SHAPER ----> CR+4th order active filter with τ = 0.5μs. - Sampling Clock (SCLK) ---> 43MHz/20 = 2.15MHz. - Data Transfer Clock (CLK) ---->43MHz. - Output Data Flow ---->20 15-bit words (16 words data + 4 words status) per Sampling Clock period (~500ns), or 43*10^6 words/sec via existent 30 meters long 17 twisted pairs cable to Finesse board. 27 T.Tsukamoto@2ndSuperBWS2004/04/23

Structure and functions of FINESSE board for ECL Barrel/CsI(Tl) INPUT DATA CONTROL BUILDER FRAME FPGA LVDS Circular IN DATA Buffer IN DATA & RAM OUT CLK L1 TRIGGER LVDS 256 x 16 bit OUT 43MHz CONTROL IN Sampling CONTROL LOGIC Clock 2.15MHz - The FINESSE board receives data from one SHAPER&ADC Barrel module (16 channels), or 64 channels per one CoPPER module. - The FINESSE board transfer to ShaperADC Barrel module 43MHz data transfer Clock and 2.15MHz sampling Clock. - Input Data Flow -->20 15-bit words (16 words data + 4 words status) per Sampling Clock period (~500ns), or 43*10^6 words/sec. - Data are continuously recorded to a circular buffer (256 16 bit words ~ 20 words x 12 samples ~ 6μs). - Under control of L1 trigger signal the predefined amount of samples for each channel are transfer to FIFO CoPPER module. 28 T.Tsukamoto@2ndSuperBWS2004/04/23

– CAMAC version ditigizer was made – FINESSE was made ==> can be final if no problems – Test is being done for CAMAC ver.+FINESSE+COPPER CAMAC ver. (4ch) for CsI(Tl) FINESSE for CsI(Tl) 29 T.Tsukamoto@2ndSuperBWS2004/04/23

Waveform sampling module for ENDCAP pure CsI (under design) ADCs FPGA 1 14+1 1 x1 TO CH1 14+1 SHAPER 1 FINESSE CYCLONE 15 x16 LVDS15 MUX EP1C3T144C8 DATA FROM FINESSE CH2 x1 SHAPER 2 L1 CONTROL LOGIC 14+1 CLK 43MHz LVDS 3 x16 CH15 CH16 TKO BUS TKO 30 Interfac FPGA 8 e - 16 Channels on TKO Board. - SHAPER: CR+4th order active filter with τ = 30ns. - Sampling rate: 43MHz to internal FIFO (256 words deep for each channel) - Output Data Flow : 160 15-bit words (10 words /channel x 16ch) for each L1 signal via existent 30 meters long 17 twisted pairs cable to FINESSE board. 30 T.Tsukamoto@2ndSuperBWS2004/04/23

Structure and functions of FINESSE board for ECL Endcap/pure CsI (under design) BUFFER LVDS FPGA DATA IN IN INPUT CLK DATA DATA 43MHz OUT L1 TRIGGER L1 OUT CONTRO LVD CONTROL IN STATUS L CONTROL LOGIC S - The FINESSE board receives data from one ShaperADC Endcap module (16 channels), or 64 channels per one CoPPER module. - The FINESSE board transfer to ShaperADC Endcap module 43MHz clock, status information and L1 trigger signal to start data transfer. - Input Data Flow ---->~ 160 14-bit words under 43MHz Clock control during ~4μs after L1 trigger signal. - After input control data are directly stored in FIFO buffer of CoPPER module. No data storage on FINESSE board. 31 T.Tsukamoto@2ndSuperBWS2004/04/23

● Summary: Belle-ECL upgrade plan for Super- KEKB – Barrel : CsI(Tl) + shorter shaping + waveform sampling – Endcap : pure CsI + PMT + waveform sampling – Hope that performance can be kept @ x20 BG ● Some degraded resolution for low energy γ 's ( 2% ==> 3.5 – 4% for 100MeV γ) – Light output will be decreased <10% by x20 radiation dose, which doesn't cause problems. ● Test is continued. 32 T.Tsukamoto@2ndSuperBWS2004/04/23