Barrel Calorimeter (EB + HB) Off-detector electronics Bob Hirosky - - PowerPoint PPT Presentation

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Barrel Calorimeter (EB + HB) Off-detector electronics Bob Hirosky - - PowerPoint PPT Presentation

Oct 23, 2023 168 likes •450 views

Barrel Calorimeter (EB + HB) Off-detector electronics Bob Hirosky HL-LHC Barrel Calorimeter L3 Manager Pre-FDR Review Fermilab, 13 th 14 th December 2018 Bob Hirosky, 13-14 Dec 2018 Pre-FDR || BCAL 1 Outline Motivation

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SLIDE 1

Barrel Calorimeter (EB + HB)

Off-detector electronics

Bob Hirosky HL-LHC Barrel Calorimeter L3 Manager Pre-FDR Review Fermilab, 13th – 14th December 2018

1 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

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SLIDE 2

2 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

Outline

  • Motivation
  • Overview of off detector / back end (BE) electronics
  • Personnel
  • Requirements
  • Barrel calorimeter processor design
  • Schedule
  • Risks
  • QA/QC
  • Costs
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SLIDE 3

3 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

Motivation: ECAL + HCAL barrel BE electronics

Both ECAL and HCAL require updates to back end electronics to accommodate increased latency/buffer requirements for L1 trigger decisions at HL-LHC In addition ECAL will require significantly more data bandwidth than the present system to support required L1 trigger performance at high luminosity running:

  • Reduce granularity / improve resolution of data for L1 trigger

decision

  • Enhanced suppression of spurious signals (increasing with

luminosity)

  • Better pulse reconstruction => energy resolution for trigger
  • Flexibility in future algorithms to optimize future detector

performance

Full details given in L2 talk

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SLIDE 4

4 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

EB HL-LHC upgrade – Barrel Calorimeter Processor (BCP)

  • Concentrate detector raw data, build trigger primitives

and transmit to L1 Trigger.

  • Receive LHC clock and distribute with high precision

to the on detector electronics.

  • Buffer and send event data to the DAQ after L1

Accept signal received by the TCDS interface.

  • Handle slow-control of the on-detector electronics via

the lpGBT interfaces.

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SLIDE 5

5 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

HB HL-LHC upgrade – BCP Back-End

EB and HB use common ATCA platform

  • Concentrate detector

raw data, build trigger primitives and transmit to L1 Trigger.

  • Receive LHC clock

and distribute to on detector electronics.

  • Buffer and send event data to the DAQ after L1 Accept signal received by

the TCDS interface.

  • Handle slow-control of the on-detector electronics
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SLIDE 6

6 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

Engineering team

Engineers:

  • Tom Gorksi, Electronic Engineer, Wisconsin. 20 years experience.

Designer of phase 1 Calo trigger board (CTP7)

  • Stephen Goadhouse, Electronic engineer, Virginia. 18 years experience.

Designer of HCAL phase 1 FE board (ngCCM) Nikitas Loukis, Electronic engineer, Notre Dame. CMS member for 6

  • years. Barrel Muon Trigger development
  • Eric Frahm, Electronic engineer, Minnesota. 20 years of experience.

Designer of HCAL phase 1 BE board (μHTR)

  • Tulio Grassi, Electronic engineer, Maryland. 15 years of experience.

Designer of HCAL phase 0 (and 1) board (HTR)

Physicists:

  • Faculty: Jessop (ND), Hirosky (UVa), Rusack (UMN), Belloni (UMD),

Orimoto (NEU)

  • Post-docs and students from each group
  • Technicians from the groups as required
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SLIDE 7

7 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

Engineering requirements

Barrel Calorimeter Requirements CMS-doc-13317

Engineering requirements specify technical details needed to achieve physics performance requirements ...

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SLIDE 8

8 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

BCP design specifications (Barrel ECAL+HCAL)

Specifications driven by CMS Document 13317:

  • Science-Engineering

(physics mission) requirements

  • Engineering (technical)

requirements

  • Interface control

requirements

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SLIDE 9

9 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

BCP baseline design

  • ATCA form factor BE

system

 2.5k 2.5 Gbps FE

control links

 10k 10 Gbps data links

  • 108 BCP modules for EB

 Trigger primitive

generation and Level 1 trigger interface

 Common CMS interface

  • TCDS, DAQ
  • 18 BCP for HB
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SLIDE 10

10 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

EB: Processing region per FPGA

ECAL Barrel Calo. (supermodule) Barrel: |η| < 1.48 36 Supermodules, 61200 crystals

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SLIDE 11

11 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

EB: Data flow and tasks

  • On BCP each FPGA concentrates FE-data

from lpGBT links

  • 300 channels are decompressed using FIFOs
  • Single crystal energy

deposit is calculated

  • Linearization
  • FIR filter
  • Peak finder
  • Amplitude to

energy LUT

  • Lateral sharing
  • Spike rejection though swiss cross or other algorithm(s)
  • Additional clustering is under consideration
  • Data are transmitted to calo L1T
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SLIDE 12

12 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

Barrel calorimeter schedule summary

V1.1 Nov 19 , 2017

MREFC Funding Start

CY18 18 CY17 17 CY19 19 CY20 20 CY21 CY22 22 CY23 23 CY24 24

Des esign gn and and Dev evel elopm

  • pmen

ent (under under op

  • per

erat ations

  • ns pr

progr

  • gram

am) Construction Project (MREFC) Produc

  • duction
  • n

CY25 25 CY26 CY16 16

CDR PDR FDR

Int’l CMS

TDR FE-PRR EDR Need- eed- by by-dat date

LHC

BCP Run un 2 Run un 3 Run un 4 LS LS 2 LS LS 3

HL-LHC Operations Start MREFC Completion

Schedu edule e Float

  • at

Pre- e-Produc

  • duction
  • n

Testing ng and and Int ntegr egrat ation

  • n

Testing ng and nd Integr egrat ation

  • n

Produc

  • duction
  • n

Sche hedu dule e Float

  • at

Pre- e-Produc

  • duction
  • n

FE BCP FE

BCP-PRR  TDR – Technical Design Report (Reviewed & Approved by LHCC 2018)  EDR – Engineering Design Review  PRR – Production Readiness Review  12 months of float from delivery to need by date= 20% of baseline duration

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SLIDE 13

13 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

BCAL Near term milestones

Milestone Date Comment Complete testjng of VFE V1 Q1 2019 CATIA V1 + commercial ASIC Complete testjng of LVR V1 Q1 2019 Compatjble with VFE V1 and FE V1 Complete testjng of FE V1 Q4 2018 GBTx version completed Decision on data compression Q1 2019 Cooling study Q1 2019 Complete testjng of BCP V1 Q2 2019 Single FPGA version Complete testjng of VFE V2 Q4 2019 CATIA V1 + LiTE-DTU V1 Complete testjng of LVR V2 Q4 2019 Compatjble with VFE V2 and FE V2 Complete testjng of FE V2 Q4 2019 lpGBT version * * This is driven by schedule of FE electronics. For BE, affects number of boards for production, no impact on BE design

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SLIDE 14

14 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

Preconstruction Schedule

Use multiple levels of FW and HW tests for risk mitigation

  • Clock distribution and FW/FPGA simulation
  • Demonstrator chains
  • Single FPGA prorotype
  • Full prototype
  • Preproduction board tests (included in construction project)
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SLIDE 15

15 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

Summary from risk register

Risk Description Impact Description RT-402- 3-01-N lGBTX optical links do not meet requirements Design of FE cards, maximum sampling rate, number of required back end cards RT-402- 3-03-N Firmware release does not meet requirements Add firmware engineer for 1-3 months to accelerate development RT-402- 3-06-N lpGBT cannot meet clock jitter specification Plan alternate design of system to accommodate additional clock fiber RT-402- 3-07-N ECAL data compression fails requirements Redesign of FE board. Increase the order of BCP boards to accommodate the additional inputs

HCAL requirements are modest compared to performance requirements for ECAL. Therefore risks are associated with ECAL BE system. Extensive technical studies and prototype cycles to verify that baseline design is capable of satisfying all performance requirements

CMS Document 12897

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SLIDE 16

16 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

EB evaluation chain

  • Use μTCA based demonstrator (CTP7): test GBT links (FE board) will

communicate properly w/ the BCP using GBT protocol (bottom picture)

  • Use (CTP7) to evaluate FE-2018 version hosting 5 GBTx chips (right picture)
  • Count transmission errors for a week w/ none recorded
  • Inject patterns to adapter boards

(VICE board) and capture them on the CTP7 (left picture) – VICE -> FE -> CTP7

  • Evaluate the jitter of the distributed

clock by the CTP7 on the FE side

Partially addresses RT-402-3-03-N FE => BE data flow

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SLIDE 17

17 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

HCAL evaluation chain uHTR

5 Gbps data link on ~20 meter MultiMode

  • ptical fibers.

CTP7 Optjcal splituer

HB FE RBX: RM1 RM2 RM3 RM4

  • The CTP7 has been

successfully used to read

  • ut data from one HB FE

box

  • FE-Data acquired by the

CTP7 were compared both to expected data, and to data acquired by a Phase 1 readout:

  • Acquired data were

compatible and in line with expectations.

  • Required clock

manager functions demonstrated

Partially addresses RT-402-3-03-N FE => BE data flow

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SLIDE 18

18 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

Resource/latency studies

Post-synthesis analysis of 300 single-crystal Trigger Primitive Generator (TGP), based on FENIX logic, indicates the KCU115 as a reasonable choice.

Partially addresses RT-402-3-07-N Test of compression scheme

Latency study including data transmission times, simulation of decompression and TGP generation.

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SLIDE 19

19 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

BCP demonstrator (BCPd)

Single-FPGA demonstrator <= include support for multiple clock distribution schemes

Partially addresses RT-402-3-06-N Test of clock distribution

Fully functional demonstrator card, with reduced channel count for first system- level testing purposes

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SLIDE 20

20 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

BCPd progress

Schematic design >90% complete. Board design (layout) in 2019Q1

Main items to finish (each ~50-80% complete):

  • Capture of overall power needs, finalize associated power distribution
  • Completion of micro-controller (ELM) and IPMC interfaces

Completion of BOM, parts symbols, footprints

  • Also NDA in progress for details on high speed links
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SLIDE 21

21 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

Progress in other areas

  • Synchronization on received data
  • Bit – alignment (SERDES factor) method
  • Channel – alignment (channel to channel) method
  • High precision clock distribution, FE synchronization
  • How to move the upstream data away from metastable states
  • Measurements of clock jitter using both cascaded PLLs

(baseline) and alternate ‘pure’ clock distribution

  • Compression
  • Recovery in case of decompression error
  • Monitoring
  • Action on synchronization failure
  • Transmission requests for LiTe-DTU (front end)
  • Fast commands with e-links
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SLIDE 22

22 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

Development steps (1/2)

  • Each BCP development cycle (demo, prototype, pre-production) will follow a

common schedule

  • BCP version specification document - 2 months
  • Schematics - 4 months
  • Layout - 3 months
  • Fabrication & assembly - 1 month
  • Initial firmware development and board verification - 3 months
  • Interface evaluation and integration with FE, DTH, Trigger - 3 months
  • + 2 months contingency
  • BCP demo goal - one FPGA on board – 2019.Q2 milestone
  • Our main goal: To develop basic interfaces, needed by the ATCA standard.
  • Board inspection: IPMC function - sufficient powering - connect and program the

FPGA - control the card - heating monitoring

  • Evaluate PCB design by performing iBERT test and recording eye diagrams.
  • Start developing communication protocols: GBT, lpGBT, async links with the trigger

– Start moving the logic in current demonstrator (utilizing CTP7) to the BCP demo

  • Implement simple pDAQ interface for testing the VFE -> FE -> BCP -> PC chain in

the lab.

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SLIDE 23

23 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

Development steps (2/2)

  • BCP prototype demo - two FPGAs board - Milestone 2020.Q3
  • Our main goal: To have a fully functional BCP and write the BCP specification

document

  • After inspection we will implement all interfaces as well as the algorithm
  • Evaluate PCB design by performing iBERT test and recording eye diagrams.
  • Development of a logic framework that will serve all common EB, HB functions
  • Optical links, control, monitoring ...
  • Pre-production - Milestone 2022.Q1
  • Our main goal: To have an optimized fully functional BCP.
  • Test the VFE -> FE -> BCP -> PC chain under test beams before final submission.
  • Finalize the BCP specification document.
  • Production - Milestone 2023.Q2
  • Evaluate the BCP board
  • Upgrade the firmware
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SLIDE 24

24 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

Barrel calorimeter processor QA/QC

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SLIDE 25

25 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

Deliverables

Item Quantity for detector Quantity for testbenches Quantity for yield spares Quantity for

  • perational

spares Total ECAL Front End (FE) Board 402.03.03.02 2448 68 245

  • 2768

ECAL Barrel Calorimeter Processor Boards* + firmware 402.03.03.(03/04/05) 112 5 5 12 134 HCAL Barrel Calorimeter Processor Boards* + firmware 402.03.04.04 18 2 2 2 24 Integration test platforms ECAL Barrel Full Prototype 402.03.03.06 Instrument ECAL wedge for full readout tests including HL-LHC front end and back end electronics

HCAL Barrel Full Prototype 402.03.04.05

Instrument HCAL wedge for full readout tests including HL-LHC front end and back end electronics

*includes associated crates/supplies for test stands

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SLIDE 26

26 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

Basis of estimate

CMS Document 12845

Breakdown of BCP cost Working on updates on component prices. Construction of single-FPGA prototye in Q1-Q2 2019 will significantly constrain estimates

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SLIDE 27

27 Pre-FDR || BCAL Bob Hirosky, 13-14 Dec 2018

Summary