Testing of Readout Electronics for Belle II Pixel Detector Jakob Haidl , Christian Koffmane, Felix Müller, Martin Ritter, Manfred Valentan Jakob Haidl 1
Pixel Detector – Belle II • Occupancy of detector ~1% • Spatial Resolution ~15µm • Two Layers of DEPFET Pixels • Distance from IP: 14mm, 22mm • 40 half ladders • Pixel size (50x55µm² and 50x85µm²) Jakob Haidl 2
Electrical Multi Chip Module – EMCM Fully functional half Test ladder without DEPFET • Technological feasibility • Probing of Signals & Voltages • Electrical Performance Jakob Haidl 3
Electrical Multi Chip Module – EMCM 4 x DCD Drain Current Digitizer Jakob Haidl 4
Electrical Multi Chip Module – EMCM 4 x DHP 4 x DCD Data Handling Processor Drain Current Digitizer Jakob Haidl 5
Electrical Multi Chip Module – EMCM 4 x DHP 4 x DCD Data Handling Processor Drain Current Digitizer 6 x Switcher Jakob Haidl 6
Electrical Multi Chip Module – EMCM 4 x DHP 4 x DCD Data Handling Processor Drain Current Digitizer Space for Matrix Test Structures 6 x Switcher Jakob Haidl 7
Electrical Multi Chip Module – EMCM 4 x DHP 4 x DCD Data Handling Processor Drain Current Digitizer Space for Matrix Test Structures Kapton Flex Cable 6 x Switcher Jakob Haidl 8
EMCM Periphery Power Patch Panel Aluminum Jig Cooling Data Patch Panel Kapton EMCM Jakob Haidl 9
Drain Current Digitizer – DCD Two cyclic Analog Digital Converter (ADC) for each channel • Receives and digitizes DEPFET currents • 256 analogue input channels • 8 digital output buses (32 channels multiplexed to 1 bus) • Bump bonded (soldered) • 3240µm x 4969µm Jakob Haidl 10
Calibration of ADCs External Current Source • linear • low noise • fast • 248µA in 65000 steps Jakob Haidl 11
ADC Transfer Curves Number of working channels Adjust Settings of ADC Digital Value (8 bit) Data Transmission Noise integral nonlinearity Dynamic range Differential depending on nonlinearity gain Input current Jakob Haidl 12
Dynamic Range for Gain Settings Gain 1 Gain 2h Rf Rs Δ I=33.2µA Δ I=20.9µA Gain 2l Gain 4 𝐻~ 𝑆 𝑔 𝑆 𝑡 Rf Rs Gain 30k Ω 30k Ω 1 30k Ω 15k Ω 2h Δ I=14.4µA Δ I=22µA 60k Ω 30k Ω 2l 60k Ω 15k Ω 4 Jakob Haidl 13
2 Bit Offset Compensation Goal • Reduce the spread of input currents • Fit into dynamic range of ADCs Input Current Dynamic Range Channels Jakob Haidl 14
2 Bit Offset Compensation Reduction of Pedestal Spread add: • 0 x IPDAC • 1 x IPDAC • 2 x IPDAC • 3 x IPDAC 0 x 0 x Input Current 1 x 1 x Dynamic Range 2 x 3 x Channels Jakob Haidl 15
2 Bit Offset Compensation Global current subtraction to reach the dynamic range Input Current Dynamic Range Channels Jakob Haidl 16
Data Transmission – DCD to DHP 8 Data Buses • 32 channels multiplexed to 1 data bus • 8 data buses for 256 channels 8 Transfer Lines per Data Bus • each data line has 8 bit • 64 transfer lines in total Jakob Haidl 17
Sampling Point sampling point wrong readings occur close to flank Global Delay Local Delay • all channels • single channel • up to 15 delay elements • up to 15 delay elements Jakob Haidl 18
Sampling Point sampling point wrong readings occur close to flank sampling at plateau correct reading Global Delay Local Delay • all channels • single channel • up to 15 delay elements • up to 15 delay elements Jakob Haidl 19
Delay Space Global Delays Local Delays Dark Blue: correct transmission Jakob Haidl 20
Data Transmission – DHP to DHH 15m Jakob Haidl 21
Data Transmission – DHP to DHH • C A: Signal Amplitude • B: Overshot Amplitude B • C: Overshot Width A Jakob Haidl 22
Data Transmission – DHP to DHH C = 0 A C B B A Jakob Haidl 23
Data Transmission – DHP to DHH C = 1 A C B B A Jakob Haidl 24
Data Transmission – DHP to DHH C = 2 A C B B A Jakob Haidl 25
Data Transmission – DHP to DHH A C = 3 C B B A Jakob Haidl 26
Summary EMCM – Half Ladder without DEPFET • ADC Transfer Curves • Dynamic Range for Gain Settings 2 Bit Offset Compensation Data Transmission ADC Settings Outlook • Operation and characterization of a small test matrix on EMCM Final modules will be tested and characterized starting from August Jakob Haidl 27
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