TUTORIAL MY FIRST HARDWARE DESIGN Tristan Gingold - - - PowerPoint PPT Presentation

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Oct 10, 2022 331 likes •646 views

TUTORIAL MY FIRST HARDWARE DESIGN Tristan Gingold - tgingold@free.fr - FOSDEM17 ITS A TALK ABOUT HARDWARE! Things like that There are many talks at FOSDEM about software. Try a different room ITS A TALK ABOUT CHIP DESIGN This

SLIDE 1

TUTORIAL MY FIRST HARDWARE DESIGN

Tristan Gingold - tgingold@free.fr - FOSDEM’17

SLIDE 2

IT’S A TALK ABOUT HARDWARE!

Things like that…

There are many talks at FOSDEM about software. Try a different room

SLIDE 3

IT’S A TALK ABOUT CHIP DESIGN

This

This

This is a PCB (Printed Circuit Board) KiCad is a tool to design boards, you also need electronic knowledge

SLIDE 4

MORE SPECIFICALLY, DIGITAL CHIPS

Analog chip

Numeric chip

See the difference ?

SLIDE 5

DESIGNING AN IC IS COMPLEX…

Netlist Power Route Place Layout Cells X-talk Clock domains DRC Timing DFT LVS STA Masks Double patterning SCE

There aren’t many OSS tools for ASICs. qflow magic VLSI

SLIDE 6

… AND VERY EXPENSIVE

ASML lithography machine Expect $$$ for the first chip…

SLIDE 7

BUT SOME ARE PROGRAMMABLE!

Normal chip FPGA

There are other kinds of programmable circuits: Gate array CPLD …

SLIDE 8

FPGA ARCHITECTURE

Programmable pad: Direction Strength Level… Programmable logic (LUT) Programmable switch box

That’s a very simple view… Most FPGAs also have PLL, memories, multipliers, or even SERDES/PCI-e blocks. See FPGA databooks

SLIDE 9

DIGITAL IS ABOUT 0 AND 1

That’s simple ! Assuming you know about binary computation

For analog design, see gnucap or spice (There are always analog parts in a circuit)

SLIDE 10

DIGITAL IS ABOUT LOGIC BASIC OPERATIONS

bbc.co.uk

Inputs Inputs Inputs NOT gate D = ~A OR gate Z = D | E Output AND gate D = B & C

SLIDE 11

COMBINE THEM!

Q = A ^ B Symbol for XOR gate

wikipedia.org

SLIDE 12

OR DO MATH (ONE BIT)

Q = A ^ B = A + B = A ~= B

wikipedia.org

A B Q 0 0 0 0 1 1 1 0 1 1 1 0

SLIDE 13

THE ADDER

S : SUM C : CARRY

wikipedia.org

Full Adder

SLIDE 14

MULTIPLE BIT ADDER

S = A + B

There are more efficient way to design large adders Search for Digital Logic Architecture

SLIDE 15

IF YOU CAN ADD, YOU CAN MULTIPLY!

A2 A1 A0 A3

A2 A1 A0 P0 P1 P2 P3 P4 P5 P6 P7

P = A * B

There are more efficient way to design multipliers

SLIDE 16

YOU CAN DESIGN ANY LOGICAL/ARITH FUNCTION

F()

Inputs Outputs

Well, many functions… But this is not very efficient (can take a lot of gates)

SLIDE 17

MORE POWERFUL: RECURSION!

F()

Inputs Outputs

In math, recursion is very powerful. In digital design, it doesn’t work directly!

SLIDE 18

TIMING SYNCHRONISATION

wikipedia.org

Do you remember the full adder ? It takes time for a signal to propagate through gates. (due to capacities). So the arrival times at S and Cout differ.

SLIDE 19

TIMING DIAGRAM

+1

What you expect: What you get:

Outputs are not available at the same time.

Thanks to http://wavedrom.com/editor.html

SLIDE 20

SYNCHRONOUS DESIGN

You can try to balance paths, but:

It’s very hard
propagation time depends on too many factors

You can use a logic that is not affected by delay variation (like gray code), but:

works only in some cases.

Rule #1:

no direct loop/feedback

So how to do ?

SLIDE 21

SYNCHRONOUS DESIGN

+1 clk

Flip Flop: update output on rising edge of the clock Clock

A B Clean

SLIDE 22

DIGITAL DESIGN

It’s a mix of:

logic gates
flip flops

It is possible to use schematic editors, but

tedious
doesn’t scale well

Use an HDL Hardware Description Language I will use VHDL

There are other way to synchronise (latch, falling edge, double edge…)

SLIDE 23

MY FIRST DESIGN BLINKING LEDS

latticesemi.com

Using OSS tools:

ghdl
yosys
arachne-pnr
iceStorm

Target: Lattice iCEstick ~ 22 euros Supported by OSS tools Leds

SLIDE 24

VHDL: EXTERNAL INTERFACE

boilerplate Comment (to not forget leds position) Input: clock

(externally generated 3Mhz)

utputs: leds

interface

SLIDE 25

INTERNALS

Internals Internal wire Process: concurrent execution, triggered on clk concurrent assignments

There are many VHDL or Verilog tutorials on the web.

SLIDE 26

SYNTHESIS

Translating (or compiling) sources to gates (netlist) First, analysing sources: Synthesis:

utput file

unit name synthesis script frontend command

SLIDE 27

PLACE & ROUTE

Allocate resources on the FPGA device input

utput

place file IC pin #

SLIDE 28

PROGRAM

Write into the FPGA flash USB interface Create the binary file: Write to flash: The FPGA is automatically reset and then load the new config

SLIDE 29

TOOLS USED

Synthesis: http://www.clifford.at/yosys/ VHDL front-end: https://github.com/tgingold/ghdlsynth-beta https://github.com/tgingold/ghdl Place and route: https://github.com/cseed/arachne-pnr iCE40 tools: http://www.clifford.at/icestorm/

SLIDE 30

TUTORIAL MY FIRST HARDWARE DESIGN

Tristan Gingold - tgingold@free.fr - FOSDEM’17

IT’S A TALK ABOUT HARDWARE!

Things like that…

IT’S A TALK ABOUT CHIP DESIGN

This

MORE SPECIFICALLY, DIGITAL CHIPS

Analog chip

Numeric chip

See the difference ?

DESIGNING AN IC IS COMPLEX…

Netlist Power Route Place Layout Cells X-talk Clock domains DRC Timing DFT LVS STA Masks Double patterning SCE

… AND VERY EXPENSIVE

BUT SOME ARE PROGRAMMABLE!

Normal chip FPGA

FPGA ARCHITECTURE

DIGITAL IS ABOUT 0 AND 1

That’s simple ! Assuming you know about binary computation

DIGITAL IS ABOUT LOGIC BASIC OPERATIONS

COMBINE THEM!

OR DO MATH (ONE BIT)

THE ADDER

MULTIPLE BIT ADDER

IF YOU CAN ADD, YOU CAN MULTIPLY!

YOU CAN DESIGN ANY LOGICAL/ARITH FUNCTION

F()

MORE POWERFUL: RECURSION!

F()

TIMING SYNCHRONISATION

Do you remember the full adder ? It takes time for a signal to propagate through gates. (due to capacities). So the arrival times at S and Cout differ.

TIMING DIAGRAM

+1

Outputs are not available at the same time.

SYNCHRONOUS DESIGN

You can try to balance paths, but:

You can use a logic that is not affected by delay variation (like gray code), but:

Rule #1:

no direct loop/feedback

So how to do ?

SYNCHRONOUS DESIGN

+1 clk

A B Clean

DIGITAL DESIGN

It’s a mix of:

It is possible to use schematic editors, but

Use an HDL Hardware Description Language I will use VHDL

MY FIRST DESIGN BLINKING LEDS

Using OSS tools:

Target: Lattice iCEstick ~ 22 euros Supported by OSS tools Leds

VHDL: EXTERNAL INTERFACE

boilerplate Comment (to not forget leds position) Input: clock

interface

INTERNALS

Internals Internal wire Process: concurrent execution, triggered on clk concurrent assignments

SYNTHESIS

Translating (or compiling) sources to gates (netlist) First, analysing sources: Synthesis:

unit name synthesis script frontend command

PLACE & ROUTE

Allocate resources on the FPGA device input

place file IC pin #

PROGRAM

Write into the FPGA flash USB interface Create the binary file: Write to flash: The FPGA is automatically reset and then load the new config

TOOLS USED

Synthesis: http://www.clifford.at/yosys/ VHDL front-end: https://github.com/tgingold/ghdlsynth-beta https://github.com/tgingold/ghdl Place and route: https://github.com/cseed/arachne-pnr iCE40 tools: http://www.clifford.at/icestorm/

QUESTIONS ?