[PPT] - 14 Gb/s AC Coupled Receiver in 90 nm CMOS Masum Hossain & Tony PowerPoint Presentation

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14 Gb/s AC Coupled Receiver in 90 nm CMOS

Masum Hossain & Tony Chan Carusone University of Toronto masum@eecg.utoronto.ca

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OUTLINE

Chip-to-Chip link overview
AC interconnects
Link modelling
ISI & sensitivity
AC Receiver architecture
Implementation in 0.18 um CMOS
Measured results
Speed and sensitivity improvement techniques
Implementation in 90nm CMOS
Measured results
Conclusion

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Achieve high speed
Small area : small coupling capacitor
High sensitivity
Achieve good FOM mW/Gb/s

Chip-to-Chip Link Overview

Goals : chip-to-chip link DC coupled serial link AC coupled serial link Proximity coupling [Miura ‘05, Drost ‘04] AC coupled link over PCB trace [Luo‘05] chip-to-chip link DC coupled serial link AC coupled serial link Proximity coupling [Miura ‘05, Drost ‘04] AC coupled link over PCB trace [Luo‘05]

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Achieves high density 3-D Integration is possible All NMOS I/O driver

1. Multi-standard integration
2. Compatible common mode
3. DC offset immune

Low speed Complexity increases Have poor FOM mW/Gb/s >10 mW/Gb/s

AC Coupled Link Overview

Input Pulse swing (mVpp) Data Rate (Gb/s) 100 200 300 400 500 1 2 3 4 5 6 7 8 9 10

Kohn ISCAS’95 Gabara JSSC’97 Drost JSSC’04 Luo JSSC’06

11 12 13 14 15

Luo CICC’06 Kim CICC’04 Miura ISSCC’07

Input Pulse swing (mVpp) Data Rate (Gb/s) 100 200 300 400 500 1 2 3 4 5 6 7 8 9 10

Kohn ISCAS’95 Kohn ISCAS’95 Gabara JSSC’97 Gabara JSSC’97 Drost JSSC’04 Drost JSSC’04 Luo JSSC’06 Luo JSSC’06

11 12 13 14 15

Luo CICC’06 Luo CICC’06 Kim CICC’04 Miura ISSCC’07

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AC Coupled Link Overview

Our goal is to increase both sensitivity and speed using standard CMOS process

Input Pulse swing (mVpp) Data Rate (Gb/s) 100 200 300 400 500 1 2 3 4 5 6 7 8 9 10

Kohn ISCAS’95 Gabara JSSC’97 Drost JSSC’04 Luo JSSC’06

11 12 13 14 15

Luo CICC’06 Kim CICC’04

0.18 um 90 nm 0.18 um 90 nm

Miura ISSCC’07

Input Pulse swing (mVpp) Data Rate (Gb/s) 100 200 300 400 500 1 2 3 4 5 6 7 8 9 10

Kohn ISCAS’95 Kohn ISCAS’95 Gabara JSSC’97 Gabara JSSC’97 Drost JSSC’04 Drost JSSC’04 Luo JSSC’06 Luo JSSC’06

11 12 13 14 15

Luo CICC’06 Luo CICC’06 Kim CICC’04

0.18 um 90 nm 0.18 um 90 nm

Miura ISSCC’07

Increase speed Increase sensitivity

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AC Coupled Link Modeling

W/o T line With 30 cm T line 20 dB/dec W/o T line With 30 cm T line 20 dB/dec

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20 mV 40 mV 80 mV 20 mV 40 mV 80 mV

C = 50 fF

ISI & Rx Sensitivity

C = 80 fF C = 150 fF

14 Gb/s input eye Coupling capacitor area ISI sensitivity requirement Coupling capacitor area ISI sensitivity requirement

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Rx Architecture

AC coupled Rx

Linear Rx Non-linear Rx Clock forwarded [Miura’05] Data recovery without clock [Drost’04,Luo’05]

8b10b code
Inductors
Not robust
Complexity & power
Timing margin
Clock distribution
Robust
Low power
Requires high speed

hysteresis

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Non-linear Clock less Rx

Hysteresis – Regenerates data from the transitions

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Hysteresis Condition : gmRL > 1
Unstable points : M,N (large gain gmRL)
Bi-Stable points : A,B (non-linear gain)

Hysteresis Architecture

Positive feedback Positive feedback

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RL

gm gm-in ( ) ( )

ut

tail L in m in L

v t I R v t g R

−

= + −

( ) ( )

in th

ut

V t V v t V << ≈ +

( ) ( )

in th

ut

V t V v t ≈ ≈

−

=> =

m th

m in

2g sensitivity 2 V V g

Latch Mode ΔVin << Vth [A-B]

Hysteresis Analysis

Itail

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RL

gm gm-in

Switching Mode ΔVin ≈ Vth [B-C]

( ) ( )

in settle

t v t V Kv t exp⎛ ⎞ = − − ⎜ ⎟ τ ⎝ ⎠

CTot

Hysteresis Analysis

m in L L Tot settle m L m L

g R R C K g R 1 g R 1

−

= τ = − −

exponential Linear

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RL

gm gm-in

( ) ( )

ut

tail L in m in L

v t I R v t g R

−

= − −

( ) ( )

in th

ut

v t V v t V >> ≈ −

Latch Mode ΔVin >> Vth [C-D]

Hysteresis Analysis

Itail

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Hysteresis Architecture

RL

gm gm-in

CTot

L Tot settle m L

R C g R 1 τ = −

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Hysteresis Design Consideration

Increase gmRL
Increase CTot
Increase power

consumption

RL

gm gm-in

CTot RL

gm gm-in

CTot

L Tot settle m L

R C g R 1 τ = −

Speed Improvement
Reduce CTot

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Condition for hysteresis : (gm2RL2)(gm3RL1) >1
gm2 buffers node VHYST from capacitive loading
RL2 , RL3 distributes the output capacitance

Improved Hysteresis Architecture

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gm-in=6.5 mS gm2 =7.1 mS gm3 =7.8 mS RL =300-ohm Rout =80-ohm

( )( )

m2 L m3 OUT

g R g R 1 3347 1 . = >

m in th th m2

2g V 40mV; 2 V V 76mV g

−

= = =

HYST L Tot

R C 18ps τ = =

Hysteresis condition:
Sensitivity & Logic levels:
Rise time:
Power Consumption: (1.8 X10) < 20 mW

10+ Gb/s Hysteresis Design

gm-in gm2 gm3

RL Rout

gm-in gm2 gm3

RL Rout

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Implementation & Measurement

150 fF Capacitance 600 um 400 um

Active area 200 um X 300 um
Only single ended testing was possible
Measured swing will be 25% of actual swing

On chip channel Off chip termination Scope

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10 Gb/s Measured eye

20 mV

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10 Gb/s Measured sequence

Error free operation verified with 127 bit pattern

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14 Gb/s Measured eye

50 mV 20 mV Rx eye Recovered eye

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Performance Summary

Process 0.18 um CMOS
Bit rate 10+ Gb/s
Output Eye amplitude 80 mVp-p differential
Coupling capacitor of 150 fF
Power consumption 20 mW
Coupling C = 80fF : improve sensitivity
Eye Amplitude > 250 mV : increase output swing
Bit Rate = 15 Gb/s : improve speed

90-nm Implementation

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Improving sensitivity

5x Improvement in sensitivity !!

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+Vth

Vth

+Vth

Vth

Bandwidth of the Pre-amp

Pre-amp requires more BW in AC coupled receivers !!! Jitter due to pre-amp (BW = 8GHz)

Slope eye [10 Gb/s] Recovered NRZ eye [10 Gb/s]

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Bandwidth of the Pre-amp

BW 8 GHz Gain 18 dB Rise Time 25 ps 14 Gb/s eye diagram 16 Gb/s eye diagram

How can we improve Jitter and ISI ??

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Speed Improvement

Improve speed by using available data transitions
How to match the latency ?
Can we have sufficient BW ?

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2 vo n v 2 2 n n

A A s 2 s ω = + ζω + ω

Speed Improvement

[Galal ’02]

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Speed Improvement

16 Gb/s eye diagram 16 Gb/s eye diagram VHYST VEQ

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Implementation in 90-nm CMOS

Each stage AV=gmRL= 1.9
Bandwidth >15 GHz
Power consumption 2mW
Total Gain: 7.6 > 5
Bandwidth = 11 GHz
Total power = 8 mW

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Implementation in 90-nm CMOS

Pre-amp Pre-amp + Slope-amp

2 GHz

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Implementation in 90-nm CMOS

10 Gb/s eye

VSLOPE VHYST 200 mV

200 mV

200 mV

200 mV

300pS 400pS 200pS 100pS VSLOPE VHYST 200 mV

200 mV

200 mV

200 mV

200 mV

200 mV

200 mV

200 mV

200 mV

200 mV

300pS 400pS 200pS 100pS

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Implementation in 90-nm CMOS

Transmitted sequence Bit period 50 ps

Arrow indicates error bits

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300 um 150 um

80 fF Pre-amp

Hysteresis

Adder

Slope Amp

Implementation in 90-nm CMOS

Active area 100 um X 300 m
Total power 32 mW

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10 Gb/s Measured eye

Slope path was turned off at 10 Gb/s 50 mV

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14 Gb/s Measured eye

Slope Path OFF Slope Path ON Vertical scale : 25 mV/div Horizontal scale : 50 ps/div Vertical scale : 50 mV/div Horizontal scale : 50 ps/div

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14 Gb/s Measured BER Bathtub

14 Gb/s recovered eye with Hysteresis only 14 Gb/s recovered eye with Hysteresis + Slope-path

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Conclusion

10+ Gb/s hysteresis circuit topology is implemented and

tested in 0.18-um CMOS process (FOM 2 mW/Gb/s)

High speed AC coupled receiver architecture is introduced:
1. Additional slope path reduces ISI at hysteresis output
2. Additional slope path reduces jitter
14 Gb/s AC coupled receiver is implemented and tested in

90-nm CMOS

FOM 1.80 mW/Gb/s @ 10 Gb/s
FOM 2.28 mW/Gb/s @ 14 Gb/s