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Schedule Date Day Class Title Chapters HW Lab Exam No. Due - - PowerPoint PPT Presentation

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Schedule Date Day Class Title Chapters HW Lab Exam No. Due date Due date 1 Dec Mon 25 Final Review LAB 8 2 Dec Tue 3 Dec Wed 26 Final Review 4 Dec Thu 5 Dec Fri Recitation HW 11 6 Dec Sat 7 Dec Sun 8 Dec Mon 27

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SLIDE 1

ECEN 301 Discussion #25 – Final Review 1

Date Day Class No. Title Chapters HW Due date Lab Due date Exam 1 Dec Mon 25 Final Review LAB 8 2 Dec Tue 3 Dec Wed 26 Final Review 4 Dec Thu 5 Dec Fri Recitation HW 11 6 Dec Sat 7 Dec Sun 8 Dec Mon 27 Final Review LAB 9 9 Dec Tue

Schedule…

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SLIDE 2

ECEN 301 Discussion #25 – Final Review 2

Summary

Jacob 6:12 12 O be wise; what can I say more?

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SLIDE 3

ECEN 301 Discussion #25 – Final Review 3

Lecture 25 – Final Review

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SLIDE 4

ECEN 301 Discussion #25 – Final Review 4

Final Exam

17 – 21 December Chapters 2 – 6, 8, 13 – 15 30 questions

 30 multiple choice (answer on bubble sheet!)

  • 1 point each

 0 long answer (show your work!)

  • 4 or 5 points each

Closed book!

 Three 3x5 cards allowed

Calculators allowed No time limit Study lecture slides and homework

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SLIDE 5

ECEN 301 Discussion #25 – Final Review 5

Final Exam Review…Overview

1. Exam 1 Review 2. Exam 2 Review 3. Binary Numbers

 Signed & Unsigned  Conversions

4. Logic Functions

 Conversions among 3 representations

5. Boolean Algebra 6. Combinational Logic 7. Sequential Logic 8. Digital to Analog Converters (DACs)

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SLIDE 6

ECEN 301 Discussion #25 – Final Review 6

Binary Numbers – Unsigned

Binary word (B): a sequence of n 1s and 0s B = bn-1bn-2…b2b1b0.b-1b-2…b-(m-1)b-m

 EX:

  • B = 10100101.1001 (n = 8, m=4)

Converting from binary (B) to decimal (D) B = bn-1bn-2…b2b1b0.b-1b-2…b-(m-1)b-m D = bn-1·2n-1 + bn-2·2n-2 + … + b1·21 + b0·20 + b-1·2-1 + b-2·2-2 + … + b-(m-1)·2-(m-1) + b-m·2-m

Binary point

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SLIDE 7

ECEN 301 Discussion #25 – Final Review 7

Binary Numbers – Unsigned

Example1: What is 0110101.01012 in decimal?

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SLIDE 8

ECEN 301 Discussion #25 – Final Review 8

Binary Numbers – Unsigned

Example1: What is 0110101.01012 in decimal?

10 4 3 2 1 1 2 3 4 5 6 2

3125 . 53 0625 . 25 . 1 4 16 32 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 1 2 01 0110101.01

6 5 4 3 2 1 0 -1-2-3 -4

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SLIDE 9

ECEN 301 Discussion #25 – Final Review 9

Binary Numbers – Signed

3 common representations for signed integers:

  • 1. Sign magnitude
  • 2. 1’s compliment
  • 3. 2’s compliment

Most common for computers

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SLIDE 10

ECEN 301 Discussion #25 – Final Review 10

Binary Numbers – Sign-Magnitude

Range: Representations

01111binary => 15decimal 11111 => -15 00000 => 0 10000 => -0

Problem

Difficult addition/subtraction

  • check signs
  • convert to positive
  • use adder or subtractor as required

How to add two sign-magnitude numbers?

  • Ex: 1 + (-4)

The MSB encodes the sign: 0 = + 1 =

1 2 1 2

1 1 n n

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SLIDE 11

ECEN 301 Discussion #25 – Final Review 11

Binary Numbers – 1’s Complement

Range: Representations

00110binary => 6decimal 11001 => -6 00000 => 0 11111 => -0

Problem

Difficult addition/subtraction

  • no need to check signs as before
  • cumbersome logic circuits
  • end-around-carry

How to add to one’s complement numbers?

  • Ex: 4 + (-3)

To negate a number, Invert it, bit-by-bit. MSB still encodes the sign: 0 = + 1 =

1 2 1 2

1 1 n n

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SLIDE 12

ECEN 301 Discussion #25 – Final Review 12

Binary Numbers – Two’s Complement

Range: Representation:

 If number is positive or zero,

  • normal binary representation, zeroes in upper bit(s)

 If number is negative,

  • start with positive number
  • flip every bit (i.e., take the one’s complement)
  • then add one

00101 (5) 01001

(9)

11010

(1’s comp) (1’s comp)

+ 1 + 1 11011 (-5)

(-9)

10110 10111

1 2 2

1 1 n n

MSB still encodes the sign: 0 = + 1 =

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SLIDE 13

ECEN 301 Discussion #25 – Final Review 13

Binary Numbers – Signed

Example2: What is the 2’s complement of 01101012 ?

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SLIDE 14

ECEN 301 Discussion #25 – Final Review 14

Binary Numbers – Signed

Example2: What is the 2’s complement of 01101012 ? 0110101 (53) 1001010 (1’s comp) + 1

(add 1)

1001011 (-53)

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SLIDE 15

ECEN 301 Discussion #25 – Final Review 15

Binary Numbers – Decimal to Binary

Positive numbers

 start with empty result  if decimal number is odd, prepend ‘1’ to result else prepend ‘0’  divide number by 2, throw away fractional part (INTEGER divide)  if number is non-zero, go back to  else you are done

Negative numbers

do above for positive version of number and negate

result.

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SLIDE 16

ECEN 301 Discussion #25 – Final Review 16

Binary Numbers – Decimal to Binary

Example3: convert -195 to 2’s complement binary notation

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SLIDE 17

ECEN 301 Discussion #25 – Final Review 17

Binary Numbers – Decimal to Binary

Example3: convert -195 to 2’s complement binary notation

1. First find positive version (195) in binary – then take 2’s complement

Is it odd? 195 1

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SLIDE 18

ECEN 301 Discussion #25 – Final Review 18

Binary Numbers – Decimal to Binary

Example3: convert -195 to 2’s complement binary notation

1. First find positive version (195) in binary – then take 2’s complement

Is it odd? 195 1 97 1

Integer division by 2: 195/2 = 97.5 → 97

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SLIDE 19

ECEN 301 Discussion #25 – Final Review 19

Binary Numbers – Decimal to Binary

Example3: convert -195 to 2’s complement binary notation

1. First find positive version (195) in binary – then take 2’s complement

Is it odd? 195 1 97 1 48

Integer division by 2: 97/2 = 48.5 → 48

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SLIDE 20

ECEN 301 Discussion #25 – Final Review 20

Binary Numbers – Decimal to Binary

Example3: convert -195 to 2’s complement binary notation

1. First find positive version (195) in binary – then take 2’s complement

Is it odd? 195 1 97 1 48 24

Integer division by 2: 48/2 = 24

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SLIDE 21

ECEN 301 Discussion #25 – Final Review 21

Binary Numbers – Decimal to Binary

Example3: convert -195 to 2’s complement binary notation

1. First find positive version (195) in binary – then take 2’s complement

Is it odd? 195 1 97 1 48 24 12

Integer division by 2: 24/2 = 12

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SLIDE 22

ECEN 301 Discussion #25 – Final Review 22

Binary Numbers – Decimal to Binary

Example3: convert -195 to 2’s complement binary notation

1. First find positive version (195) in binary – then take 2’s complement

Is it odd?

195 1 97 1 48 24 12 6

Integer division by 2: 12/2 = 6

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SLIDE 23

ECEN 301 Discussion #25 – Final Review 23

Binary Numbers – Decimal to Binary

Example3: convert -195 to 2’s complement binary notation

1. First find positive version (195) in binary – then take 2’s complement

Is it odd?

195 1 97 1 48 24 12 6 3 1

Integer division by 2: 6/2 = 3

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SLIDE 24

ECEN 301 Discussion #25 – Final Review 24

Binary Numbers – Decimal to Binary

Example3: convert -195 to 2’s complement binary notation

1. First find positive version (195) in binary – then take 2’s complement

Is it odd?

195 1 97 1 48 24 12 6 3 1 1 1

Integer division by 2: 3/2 = 1.5 → 1

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SLIDE 25

ECEN 301 Discussion #25 – Final Review 25

Binary Numbers – Decimal to Binary

Example3: convert -195 to 2’s complement binary notation

1. First find positive version (195) in binary – then take 2’s complement

Is it odd?

195 1 97 1 48 24 12 6 3 1 1 1

Integer division by 2: 1/2 = 0.5 → 0

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SLIDE 26

ECEN 301 Discussion #25 – Final Review 26

Binary Numbers – Decimal to Binary

Example3: convert -195 to 2’s complement binary notation

1. First find positive version (195) in binary – then take 2’s complement

Is it odd?

195 1 97 1 48 24 12 6 3 1 1 1

0110000112 2’s complement 1001111012

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SLIDE 27

ECEN 301 Discussion #21 – Boolean Algebra 27

Hexadecimal Notation

Binary is hard to read and write by hand Hexadecimal is a common alternative

16 digits are 0123456789ABCDEF

0100 0111 1000 1111 = 0x478F 1101 1110 1010 1101 = 0xDEAD 1011 1110 1110 1111 = 0xBEEF 1010 0101 1010 0101 = 0xA5A5

Binary Hex Dec

0000 0 0001 1 1 0010 2 2 0011 3 3 0100 4 4 0101 5 5 0110 6 6 0111 7 7 1000 8 8 1001 9 9 1010 A 10 1011 B 11 1100 C 12 1101 D 13 1110 E 14 1111 F 15 0x is a common prefix for writing numbers which means hexadecimal

1. Separate binary code into groups

  • f 4 bits (starting from the right)

2. Translate each group into a single hex digit

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SLIDE 28

ECEN 301 Discussion #25 – Final Review 28

Binary Numbers – Hexadecimal

Example4: convert 0111010100011110100110101112 to hexadecimal notation

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SLIDE 29

ECEN 301 Discussion #25 – Final Review 29

Binary Numbers – Hexadecimal

Example4: convert 0111010100011110100110101112 to hexadecimal notation

011101010001111010011010111

7

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SLIDE 30

ECEN 301 Discussion #25 – Final Review 30

Binary Numbers – Hexadecimal

Example4: convert 0111010100011110100110101112 to hexadecimal notation

011101010001111010011010111

7 D

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SLIDE 31

ECEN 301 Discussion #25 – Final Review 31

Binary Numbers – Hexadecimal

Example4: convert 0111010100011110100110101112 to hexadecimal notation

011101010001111010011010111

7 4 D

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SLIDE 32

ECEN 301 Discussion #25 – Final Review 32

Binary Numbers – Hexadecimal

Example4: convert 0111010100011110100110101112 to hexadecimal notation

011101010001111010011010111

7 4 D F

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SLIDE 33

ECEN 301 Discussion #25 – Final Review 33

Binary Numbers – Hexadecimal

Example4: convert 0111010100011110100110101112 to hexadecimal notation

011101010001111010011010111

7 4 D F 8

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SLIDE 34

ECEN 301 Discussion #25 – Final Review 34

Binary Numbers – Hexadecimal

Example4: convert 0111010100011110100110101112 to hexadecimal notation

011101010001111010011010111

7 4 D F 8 A

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SLIDE 35

ECEN 301 Discussion #25 – Final Review 35

Binary Numbers – Hexadecimal

Example4: convert 0111010100011110100110101112 to hexadecimal notation

011101010001111010011010111

7 4 D F 8 A 3

NB: add a leading zero to complete 4 bits

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SLIDE 36

ECEN 301 Discussion #25 – Final Review 36

Binary Numbers – Hexadecimal

Example4: convert 0111010100011110100110101112 to hexadecimal notation

011101010001111010011010111

0x3A8F4D7

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SLIDE 37

ECEN 301 Discussion #25 – Final Review 37

Binary Numbers

Example5: Complete the following table

Unsigned Sign-magitude 1’s complement 2’s complement HEX 01100110 11101011 93

  • 93
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SLIDE 38

ECEN 301 Discussion #25 – Final Review 38

Binary Numbers

Example5: Complete the following table

Unsigned Sign-magitude 1’s complement 2’s complement HEX 01100110 102 102 102 102 0x66 11101011 235

  • 107
  • 20
  • 21

0xEB 93 01011101 01011101 01011101 01011101 0x5D

  • 93

NA 11011101 10100010 10100011 0xA3

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SLIDE 39

ECEN 301 Discussion #25 – Final Review 39

Logic Functions

3 different ways to represent logic functions:

1. Equation: a mathematical representation of a logic function

sab b a s ab s b a s

  • ut

Final logic output Each letter variable represents a top-level input to the logic function Mathematical operations (i.e. addition and multiplication) are boolean algebra operations A bar over a variable represent an inverting or a NOT operation

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SLIDE 40

ECEN 301 Discussion #25 – Final Review 40

Logic Functions

3 different ways to represent logic functions:

2. Gates: a visual block representation of the function

Four 3-input AND gates feeding into one 4-input OR gate Top-level inputs Final output

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SLIDE 41

ECEN 301 Discussion #25 – Final Review 41

Logic Functions

3 different ways to represent logic functions:

3. Truth Table: indicates what the

  • utput will be for every

possible input combination

A B C Z

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

If there are n inputs (left-hand columns) there will be 2n entries (rows) in the table EX: 3 inputs require 23 = 8 rows There will always be at least one output (right-hand columns) For each input combination (row)

  • utput(s) will be

either 0 or 1

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SLIDE 42

ECEN 301 Discussion #25 – Final Review 42

Logic Functions – Gates

Type Symbol Equation Truth Table

NOT AND OR

IN OUT

B A OUT

IN OUT

1 1

A B OUT

1 1 1 1 1

B A OUT

A B OUT

1 1 1 1 1 1 1

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SLIDE 43

ECEN 301 Discussion #25 – Final Review 43

Logic Functions – Gates

Type Symbol Equation Truth Table

NAND NOR

B A OUT

A B OUT

1 1 1 1 1 1 1

B A OUT

A B OUT

1 1 1 1 1

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SLIDE 44

ECEN 301 Discussion #25 – Final Review 44

Logic Functions – Translation

B A

Logic Equations Logic Gates Truth Tables

These are three different ways of representing logical information You can convert any

  • ne of them to any other

A B OUT

1 1 1 1 1 1 1

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SLIDE 45

ECEN 301 Discussion #25 – Final Review 45

Equations to Gates

s a b y

y

b a s

y

OR

b a s y

OR

) NOT( AND AND ) NOT( b a s y

b a s

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SLIDE 46

ECEN 301 Discussion #25 – Final Review 46

Logic Functions – Gates to Equations

  • ut

b a s b a s b a s b a s

) ( ) ( ) ( ) ( b a s b a s b a s b a s

  • ut

sab b a s ab s b a s

  • ut

OR

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SLIDE 47

ECEN 301 Discussion #25 – Final Review 47

Logic Functions – Truth Tables to Gates

Each row of truth table is an AND gate Each output column is an OR gate

S A B OUT

0 0 0 0 1 0 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1

  • ut

s a b s a b s a b s a b

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SLIDE 48

ECEN 301 Discussion #25 – Final Review 48

Logic Functions – Truth Table to Equations

Write out truth table a combination of AND’s and OR’s

 equivalent to gates  easily converted to gates S A B OUT

0 0 0 0 1 0 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1

sab b a s ab s b a s

  • ut
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SLIDE 49

ECEN 301 Discussion #25 – Final Review 49

Logic Functions – Equations to Truth Tables

For each AND term

fill in the proper row on the truth table

S A B OUT

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

sab b a s ab s b a s

  • ut
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SLIDE 50

ECEN 301 Discussion #25 – Final Review 50

Boolean Algebra – Rules

Z X Y X Z X Z Y Y X Y X Y X X Z Y X Z X Y X X Y X X X Z X X . 19 . 18 ) ( ) ( . 17 ) ( . 6 1 . 15

X X X X X X X X X X X X X X X X X X . 9 . 8 . 7 1 . 6 . 5 1 . 4 . 3 1 1 . 2 . 1

Z X Y X Z Y X Z Y X Z Y X Z Y X Z Y X X Y Y X X Y Y X ) ( . 14 ) ( ) ( . 13 ) ( ) ( . 12 . 11 . 10

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SLIDE 51

ECEN 301 Discussion #25 – Final Review 51

Boolean Algebra – DeMorgan’s Law

B A B A B A B A

To distribute the bar, change the operation.

NOR Symbols NAND Symbols

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SLIDE 52

ECEN 301 Discussion #25 – Final Review 52

Boolean Algebra

Example6: simplify the following function

ACD BCD BD A D B A OUT

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SLIDE 53

ECEN 301 Discussion #25 – Final Review 53

Boolean Algebra

Example6: simplify the following function

C A D OUT D A CD OUT D A B CD OUT BCD CD D A OUT BCD C A D OUT BCD AC A D OUT ACD BCD D A OUT ACD BCD B B D A OUT ACD BCD BD A D B A OUT 14 Rule 2 Rule ) 1 ( 14 Rule 14 Rule 18 Rule 14 Rule 4 Rule 14 Rule

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SLIDE 54

ECEN 301 Discussion #25 – Final Review 54

Boolean Algebra

Example7: Simplify the equation created by the following truth table

A B C Z

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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SLIDE 55

ECEN 301 Discussion #25 – Final Review 55

Boolean Algebra

Example7: Simplify the equation created by the following truth table

A B C Z

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

ABC C AB C B A C B A BC A C B A Z

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SLIDE 56

ECEN 301 Discussion #25 – Final Review 56

Boolean Algebra

Example7: Simplify the equation created by the following truth table

A B C Z

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

C A Z A C A Z B B A C A Z AB B A C A Z C C AB C C B A B B C A Z ABC C AB C B A C B A BC A C B A Z

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SLIDE 57

ECEN 301 Discussion #25 – Final Review 57

Boolean Algebra

Example8: Determine the truth table

A B C Z

? 1 ? 1 ? 1 1 ? 1 ? 1 1 ? 1 1 ? 1 1 1 ?

A B C Z

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SLIDE 58

ECEN 301 Discussion #25 – Final Review 58

Boolean Algebra

Example8: Determine the truth table

A B C x1 Z

? 1 ? 1 1 ? 1 1 1 ? 1 1 ? 1 1 1 ? 1 1 1 ? 1 1 1 1 ?

A B C Z

B A x1

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SLIDE 59

ECEN 301 Discussion #25 – Final Review 59

Boolean Algebra

Example8: Determine the truth table

A B C x1 x2 Z

1 ? 1 1 ? 1 1 1 ? 1 1 1 ? 1 1 1 ? 1 1 1 1 ? 1 1 1 1 ? 1 1 1 1 ?

A B C Z

B A x1

C B BC x2

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SLIDE 60

ECEN 301 Discussion #25 – Final Review 60

Boolean Algebra

Example8: Determine the truth table

A B C x1 x2 x3 Z

1 ? 1 1 1 ? 1 1 1 ? 1 1 1 1 ? 1 1 1 1 ? 1 1 1 1 1 ? 1 1 1 1 1 ? 1 1 1 1 1 ?

A B C Z

B A x1 C A x3

C B BC x2

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SLIDE 61

ECEN 301 Discussion #25 – Final Review 61

Boolean Algebra

Example8: Determine the truth table

A B C x1 x2 x3 Z

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

A B C Z

B A x1 C A x3 C A BC B A Z

C B BC x2

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SLIDE 62

ECEN 301 Discussion #25 – Final Review 62

Boolean Algebra

Example8: Determine the truth table

A B C x1 x2 x3 Z

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

B C A C B C A C B A C A C B A B B C A C AB C B A C B A C A BC B A Z

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SLIDE 63

ECEN 301 Discussion #25 – Final Review 63

Combinational Logic – Decoders

Decode the input and signify its value by raising just one of its

  • utputs.

A decoder with n inputs has 2n outputs

X Y Z W

2-to-4 Decoder

A B W X Y Z

DECODER Symbol

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SLIDE 64

ECEN 301 Discussion #25 – Final Review 64

Combinational Logic – Decoders

Write the truth table

X Y Z W

A B W X Y Z

1 1 1 1 1 1 1 1

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SLIDE 65

ECEN 301 Discussion #25 – Final Review 65

Combinational Logic – Multiplexors

Connect one of its inputs to its output according to select signals Useful for selecting one from a collection of data inputs. Usually has 2n inputs and n select lines.

A B S C

1

MULTIPLEXOR Symbol

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SLIDE 66

ECEN 301 Discussion #25 – Final Review 66

Combinational Logic – Multiplexors

Write the truth table

A B S C

1

MULTIPLEXOR Symbol

A B S C

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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SLIDE 67

ECEN 301 Discussion #25 – Final Review 67

Sequential Logic – SR Latch

SR Latch with additional inputs:

 Enable (E) – S and R can only change Q when E is 1  Preset (PRE) – regardless of S, R, or E, put Q to 1 when PRE is 1  Clear (CLR) – regardless of S, R, E, or PRE, put Q to 0 when CLR is 1

S Q R E

PRE CLR

E S R PRE CLR Q Precedence:

1. If CLR = 1, Q = 0 2. If PRE = 1, Q = 1 3. If E = 1, Q is set based on SR:

  • If S = 0 and R = 0, Q = held
  • If S = 0 and R = 1, Q = 0
  • If S = 1 and R = 0, Q = 1
  • If S = 1 and R = 1, Q = unstable

4. Else Q is held SR can only change Q only in blue regions (where E = 1) BUT CLR and PRE will change Q ANYTIME

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SLIDE 68

ECEN 301 Discussion #25 – Final Review 68

Sequential Logic – D Latch

D Latch has only 2 states:

 Set (set Q to 1): D = 1  Reset (reset Q to 0): D = 0

D Latch with enable (E):

 Q can only change when E = 1 E D Qnew

Qold 1 Qold 1 1 1 1 D Q E S Q R E D E

E D Q

D can only change Q only in blue regions (where E = 1)

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SLIDE 69

ECEN 301 Discussion #25 – Final Review 69

Sequential Logic – D Flip-Flop

D FF: 2 SR latches in master/slave configuration. The

  • utput (Q) changes on the rising clock edge

D CLK Qnew

1 1 D Q

CLK

S Q R S Q R Q E E CLK D Q Master Slave

CLK D Q

D can only change Q only on rising clock edge (arrows)

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SLIDE 70

ECEN 301 Discussion #25 – Final Review 70

Sequential Logic – JK Flip-Flop

JK FF: 2 SR latches in master/slave configuration. The output (Q) changes on the falling clock edge

J K CLK Qnew

Qold 1 1 1 1 1 Qold

JK FF has 4 allowed states:

 Present state (keep Q as is): J = 0, K = 0  Reset (reset Q to 0): J = 0, K = 1  Set (set Q to 1): J = 1, K = 0  Toggle (set Q to Q): J = 1, K = 1

S Q R S Q R Q E E CLK J Q Q K J Q

CLK

K Indicates falling clock edge

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SLIDE 71

ECEN 301 Discussion #25 – Final Review 71

Sequential Logic – T Flip-Flop

T FF: JK FF with J and K inputs connected

T CLK Qnew

Qold 1 Qold

T FF has 2 allowed states:

 Present state (keep Q as is): T = 0  Toggle (set Q to Q): T = 1

CLK T Q J Q

CLK

K T Q

CLK

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SLIDE 72

ECEN 301 Discussion #25 – Final Review 72

Sequential Logic – Digital Counters

Ripple counter: with N bits, cycles through the numbers from 0 to 2N – 1

N JK FFs cascaded together to produce an N-bit up counter

CLK J Q

CLK

K J Q

CLK

K J Q

CLK

K 1 1 1 B2 B1 B0 NB: for 3-bit counter we need 3 FFs CLK B0 B1 B2

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SLIDE 73

ECEN 301 Discussion #25 – Final Review 73

Sequential Logic – Digital Counters

Synchronous counter: with N bits, cycles through the numbers from 0 to 2N – 1

Input clock drives all FFs simultaneously

T Q

CLK

T Q

CLK

T Q

CLK

CLK 1 B0 B1 B2 CLK B0 B1 B2

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SLIDE 74

ECEN 301 Discussion #25 – Final Review 74

Sequential Logic

Example9: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles

CLK

T Q

CLK

J Q

CLK

K D Q

CLK

Q2 Q1 Q0

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SLIDE 75

ECEN 301 Discussion #25 – Final Review 75

Sequential Logic

Example9: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles

CLK

T CLK Qnew

Qold 1 Qold

D CLK Qnew

1 1

J K CLK Qnew

Qold 1 1 1 1 1 Qold

1 1 1

1. Set outputs to 000 2. Based on output values change FF inputs 3. On each clock cycle: a) change FF

  • utputs based on

inputs b) Change FF inputs based on new

  • utputs

T Q

CLK

J Q

CLK

K D Q

CLK

Q2 Q1 Q0

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SLIDE 76

ECEN 301 Discussion #25 – Final Review 76

Sequential Logic

Example9: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles

CLK

T CLK Qnew

Qold 1 Qold

D CLK Qnew

1 1

J K CLK Qnew

Qold 1 1 1 1 1 Qold 1. Set outputs to 000 2. Based on output values change FF inputs 3. On each clock cycle: a) change ALL FF

  • utputs based on

inputs T Q

CLK

J Q

CLK

K D Q

CLK

Q2 Q1 Q0

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SLIDE 77

ECEN 301 Discussion #25 – Final Review 77

Sequential Logic

Example9: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles

CLK

T CLK Qnew

Qold 1 Qold

D CLK Qnew

1 1

J K CLK Qnew

Qold 1 1 1 1 1 Qold

1 1 1

1. Set outputs to 000 2. Based on output values change FF inputs 3. On each clock cycle: a) change ALL FF

  • utputs based on

inputs b) Change ALL FF inputs based on new outputs T Q

CLK

J Q

CLK

K D Q

CLK

Q2 Q1 Q0

slide-78
SLIDE 78

ECEN 301 Discussion #25 – Final Review 78

Sequential Logic

Example9: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles

CLK

Cycle Q2 Q1 Q0 start

T CLK Qnew

Qold 1 Qold

D CLK Qnew

1 1

J K CLK Qnew

Qold 1 1 1 1 1 Qold

1 1 1

Inputs changed due to outputs

T Q

CLK

J Q

CLK

K D Q

CLK

Q2 Q1 Q0

slide-79
SLIDE 79

ECEN 301 Discussion #25 – Final Review 79

Sequential Logic

Example9: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles

CLK

Cycle Q2 Q1 Q0 start 1 1 1

T CLK Qnew

Qold 1 Qold

D CLK Qnew

1 1

J K CLK Qnew

Qold 1 1 1 1 1 Qold

1 1 1

1 1 1

Outputs change on new clock cycle

T Q

CLK

J Q

CLK

K D Q

CLK

Q2 Q1 Q0

slide-80
SLIDE 80

ECEN 301 Discussion #25 – Final Review 80

Sequential Logic

Example9: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles

CLK

Cycle Q2 Q1 Q0 start 1 1 1 1

T CLK Qnew

Qold 1 Qold

D CLK Qnew

1 1

J K CLK Qnew

Qold 1 1 1 1 1 Qold

1 1 1

1 1 1 1 1

Inputs changed due to outputs

T Q

CLK

J Q

CLK

K D Q

CLK

Q2 Q1 Q0

slide-81
SLIDE 81

ECEN 301 Discussion #25 – Final Review 81

Sequential Logic

Example9: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles

CLK

Cycle Q2 Q1 Q0 start 1 1 1 2 1

T CLK Qnew

Qold 1 Qold

D CLK Qnew

1 1

J K CLK Qnew

Qold 1 1 1 1 1 Qold

1

1 1 1 1 1

Outputs change on new clock cycle

T Q

CLK

J Q

CLK

K D Q

CLK

Q2 Q1 Q0

slide-82
SLIDE 82

ECEN 301 Discussion #25 – Final Review 82

Sequential Logic

Example9: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles

CLK

Cycle Q2 Q1 Q0 start 1 1 1 2 1

T CLK Qnew

Qold 1 Qold

D CLK Qnew

1 1

J K CLK Qnew

Qold 1 1 1 1 1 Qold

1

1 1 1

T Q

CLK

J Q

CLK

K D Q

CLK

Q2 Q1 Q0 Inputs changed due to outputs

slide-83
SLIDE 83

ECEN 301 Discussion #25 – Final Review 83

Sequential Logic

Example9: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles

CLK

Cycle Q2 Q1 Q0 start 1 1 1 2 1 3 1

T CLK Qnew

Qold 1 Qold

D CLK Qnew

1 1

J K CLK Qnew

Qold 1 1 1 1 1 Qold

1

1 1 1

T Q

CLK

J Q

CLK

K D Q

CLK

Q2 Q1 Q0 Outputs change on new clock cycle

slide-84
SLIDE 84

ECEN 301 Discussion #25 – Final Review 84

Sequential Logic

Example9: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles

CLK

Cycle Q2 Q1 Q0 start 1 1 1 2 1 3 1

T CLK Qnew

Qold 1 Qold

D CLK Qnew

1 1

J K CLK Qnew

Qold 1 1 1 1 1 Qold

1

1 1 1

T Q

CLK

J Q

CLK

K D Q

CLK

Q2 Q1 Q0 Inputs changed due to outputs

slide-85
SLIDE 85

ECEN 301 Discussion #25 – Final Review 85

Sequential Logic

Example9: Assuming the outputs of the following circuit start in a 000 state, determine the outputs for 4 clock cycles

CLK

Cycle Q2 Q1 Q0 start 1 1 1 2 1 3 1 4 1 1

T CLK Qnew

Qold 1 Qold

D CLK Qnew

1 1

J K CLK Qnew

Qold 1 1 1 1 1 Qold

1 1

1 1 1

T Q

CLK

J Q

CLK

K D Q

CLK

Q2 Q1 Q0 Outputs change on new clock cycle

slide-86
SLIDE 86

ECEN 301 Discussion #25 – Final Review 86

Digital to Analog Converter (DAC)

DAC: converts an unsigned binary word to an analog output voltage or current

Resolution δv: minimum step size by which the

  • utput voltage (or current) can increment

Output voltage va: the analog value represented by the binary word B

  • EX: let n=4

va = (23·b3 + 22·b2 + 21·b1 + 20·b0)δv Max output voltage vaMax: the maximum analog value

  • EX: let n=4

vaMax = (23 + 22 + 21 + 20)δv

= (2n – 1) δv

slide-87
SLIDE 87

ECEN 301 Discussion #24 – DAC 87

Digital to Analog Converter (DAC)

Building a DAC: use a summing amplifier

– + + vo –

+ – + – + –

RSn RS2 RS1 vSn vS2 vS1 RF

– + + va –

R1 Rn-2 Rn-1 RF R0 vin bn-1 bn-2 b1 b0

Summing amplifier DAC

slide-88
SLIDE 88

ECEN 301 Discussion #25 – Final Review 88

Digital to Analog Converter (DAC)

Building a DAC:

the analog output (va) is proportional to the binary word B

1

2

n i i i in F a

b v R R v

– + + va –

R1 Rn-2 Rn-1 RF R0 vin bn-1 bn-2 b1 b0

1 n i in i i F a

v b R R v

i i

R R 2

Choose THUS

vsi in summing amplifier

slide-89
SLIDE 89

ECEN 301 Discussion #25 – Final Review 89

Digital to Analog Converter (DAC)

Example10: find the smallest resolution δv of an 8-bit DAC vaMax = 12V

– + + va –

R1 Rn-2 Rn-1 RF R0 vin bn-1 bn-2 b1 b0

slide-90
SLIDE 90

ECEN 301 Discussion #25 – Final Review 90

Digital to Analog Converter (DAC)

Example10: find the smallest resolution δv of an 8-bit DAC vaMax = 12V

mV v v v v v

n a a n a

1 . 47 1 2 12 1 2 1 2

8 min max max – + + va –

R1 Rn-2 Rn-1 RF R0 vin bn-1 bn-2 b1 b0

slide-91
SLIDE 91

ECEN 301 Discussion #25 – Final Review 91

Digital to Analog Converter (DAC)

Example11: find the resistor values for a DAC with: range = 15V δv = 1V vin = 5V RF = 2kΩ

– + + va –

R1 Rn-2 Rn-1 RF R0 vin bn-1 bn-2 b1 b0

slide-92
SLIDE 92

ECEN 301 Discussion #25 – Final Review 92

Digital to Analog Converter (DAC)

Example11: find the resistor values for a DAC with: range = 15V δv = 1V vin = 5V RF = 2kΩ

– + + va –

R1 Rn-2 Rn-1 RF R0 vin bn-1 bn-2 b1 b0

4 4 2 log 1 1 / 15 log 2 log 1 / ) ( log

min max

v v v n

a a

slide-93
SLIDE 93

ECEN 301 Discussion #25 – Final Review 93

Digital to Analog Converter (DAC)

Example11: find the resistor values for a DAC with: range = 15V δv = 1V vin = 5V RF = 2kΩ

– + + va –

R1 Rn-2 Rn-1 RF R0 vin bn-1 bn-2 b1 b0

k v v R R v R R v b v R R v

n in a F n in F a n i i i in F a

10 1 2 5 15 10 2 1 2 1 2 2

4 3 max max 1

slide-94
SLIDE 94

ECEN 301 Discussion #25 – Final Review 94

Digital to Analog Converter (DAC)

Example11: find the resistor values for a DAC with: range = 15V δv = 1V vin = 5V RF = 2kΩ

i i

R R 2

– + + va –

R1 Rn-2 Rn-1 RF R0 vin bn-1 bn-2 b1 b0

k R R 5 2 10 2

3 1 1

k R R 5 . 2 4 10 2

3 2 2

k R R 25 . 1 8 10 2

3 3 3