[PPT] - Logically Determined Design and Flow Computing with With NULL PowerPoint Presentation

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Logically Determined Design and Flow Computing with With NULL Convention Logic

First Principles Karl Fant Feb, 2015 Materials of this conversation, slides and circuit movie, can be downloaded from karlfant.net/ytvideo

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The NULL Convention

Given an element with two distinct states such as high and low voltage on an electronic wire we assign one state to mean “data” and the other state to mean “not data”, which we will call

NULL. This is in contrast to assigning both states a data meaning such as 0,1 or True, False.

The Multi-rail Convention

With only one data state data variables will be multi-rail encoded. A binary variable will be dual-rail encoded with two wires, one meaning 0 the other meaning 1, only one of which will be data at a time.

The Completeness Convention

We define patterns of each state that represent completeness. Consider the output of a dual- rail ripple carry adder which begins with all rails null. Inputs transition to data and output rails begin transitioning to data. When the add is done exactly one rail of each output dual-rail variable has transitioned to data which is a data state completeness pattern upon the occurrence

f which the input can begin transitioning to null. All output rails transitoned to null is a null

state completeness pattern upon the occurrence of which the input can begin transitioning to data and so on... Page 2

data flow completeness (done) (empty) null flow completeness (empty) null flow completeness (empty) null flow completeness (empty) null flow completeness data flow completeness (done) data flow completeness (done)

SLIDE 3

Logic operators with a completeness threshold for DATA and a completeness threshold for NULL:

transitions its output to DATA only when its data threshold is met,
transitions its output to NULL only when its input is completely NULL and
maintains its output when its input is between the two thresholds

D N D N N D – –

NULL Convention Logic (NCL)

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D D N DN DD – – N NN ND – – – – D DN DD – – NN ND – – – – – – N – – – – DN DD NN ND – – – no transition

2 0f 2 3 0f 3 2 0f 3 4 0f 4 3 0f 4

D DN DD D D NN ND – – – D – – N – – – – DN DD NN ND D – D D N DN DD – D N NN ND – – – D 3 3 3 3 3 3 3 3 3 3 3 2 3 2 4 3

A Dual threshold logic with state holding behavior.

NULL completeness (empty), awaiting Data transition NULL transitioning begins DATA transitioning begins DATA completeness (threshold met),

utput to DATA (done)

awaiting NULL transition NULL completeness (threshold met),

utput to NULL (empty)

awaiting Data transition

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NCL Dual Threshold Logic Functions

14. AB + AC + AD + BCD
9. A + B + C + D
10. AB + AC + AD + BC + BD + CD
11. ABC + ABD + ACD + BCD
12. ABCD
13. A + BC + BD + CD
2. A + B
3. AB
4. A + B + C
5. AB + BC + AC
8. AB + AC
7. A + BC
1. A
6. ABC
15. ABC + ABD + ACD
16. A + BCD
17. AB + AC + AD
18. A + B + CD
19. AB + AC + AD + BC + BD
20. AB + ACD + BCD
21. ABC + ABD
22. A + BC + BD
23. AB + ACD
24. AB + AC + AD + BC
25. AB + AC + BCD
26. AB + CD
27. AB + BC + AD
28. AC + BC + AD + BD

A A B 2 A B 1 C D A B 1 C D A B 2 C D A B 3 C D A B 4 C D A B 3 D C A B 5 D C A B 4 D C A B 3 D C A B 2 C D A B 4 C D A B 3 C D A B 4 C D A B 3 C D A B 5 D C D A B 4 D C D A B 5 C A B 2 A B C 1 A B C 3 A B C 3 A B C 2 C D A B 2

TH12 TH22 TH13 TH23 TH14 TH23W2 TH33 TH33W2 TH24 TH34 TH44 TH24W2 TH34W2 TH24W22 TH34W22 TH34W3 TH34W32 TH44W322 TH44W2 TH44W22 TH44W3 TH54W22 TH54W32 TH54W322

2 2 1 A B C D 1 1 2 A B C D 2 2 1 A B C D 2

THAND THCOMP THXOR

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NULL 1 2 3 4 5 6 7 8 9 0 N D N N N N N N N N N N N D N N N N N N N N N N N D N N N N N N N N N N N D N N N N N N N N N N N D N N N N N N N N N N N D N N N N N N N N N N N D N N N N N N N N N N N D N N N N N N N N N N N D N N N N N N N N N N N D #1 #2 #3 #4 #5 #6 #7 #8 #9 #10 Wire numeric base 10 meanings N D N N N D #1 #2 NULL TRUE FALSE Wire Logical meanings

With only one data value, an M value variable is expressed with M rails only one of which will express its DATA value at a time.

N D N N N N D N N N N D #1 #2 #3 NULL Animal Vegetable Mineral Wire general meanings N D N N N N D N N N N D #1 #2 #3 NULL Select A Select B Select C Wire control meanings N D N N N N N D N N N N N D N N N N N D #1 #2 #3 #4 NULL 0 1 2 3 Wire numeric base 4 meanings N D N N N N N D N N N N N D N N N N N D #1 #2 #3 #4 Wire

ther meanings

NULL First Second Third Fourth N D N N N D #1 #2 NULL 0 1 Wire numeric base 2 meanings

The multi-rail convention

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Movie discusion

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Self Coordination: The Oscillation The expression is purely in terms of logical relationships

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scillation period 20 gate delays

data path latency 7 gate delays 1 oscillation 26 cells 11-13 signal transitions

The oscillation Link coordinates flow from oscillation to oscillation When linked oscillations present data to a link it will pass a data wave and maintain the data wave until the oscillations present null When linked oscillations present null to a link it will pass a null wave and maintain the null wave until the oscillations present data

1 1 1

00 01 10 11 00 01 10 11

1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 2 2 2 2

links link closure closure link

1 1 B A 1 CI 1 S CO 1

closure

1 1

00 01 10 11

2 2 2 2 1

closure closure closure circuit input boundary

half-adder half-adder OR

Completeness is fed back with inversion (closure) creating an oscillation with:

one or more sources,
a completeness flow path and
one or more destinations

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Page 8 Since the combinational expression and the link are both in terms of logical relations they can be optimized together

1 1

00 01 10 11 00 01 10 11

1

2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2

link closure closure link

1 S CO 1

half-adder half-adder

closure

1 1

00 01 10 11

OR 3 3 3 3 1

links

1 2 2 2 2 2 2 1 1

1 1 B A 1 CI

closure closure closure

integrate combinational logic and link

scillation period 18 gate delays

data path latency 6 gate delays 1 oscillation 24 cells 10-12 signal transitions

1 1

00 01 10 11 00 01 10 11

1

2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2

link closure closure link

1 2 2 2 2 2 2 1 1

links

1 1 B A 1 CI 1 S CO 1

closure

1 1

00 01 10 11

2 2 2 2 1

closure closure closure

half-adder half-adder OR

scillation period 20 gate delays

data path latency 7 gate delays 1 oscillation 26 cells 11-13 signal transitions

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finer oscillation granularity

1 1

00 01 10 11 00 01 10 11

1

2 3 3 3 3 3 3 3 3 1 1 1 1 1 1 2 2

link closure link

1 S CO 1

half-adder half-adder

closure

1 1

00 01 10 11

OR 3 3 3 3 1 1 2 2 2 2 2 2 1 1

links

1 1 B A 1 CI

closure closure closure

1 2 2

link

1 1 3 1 2 2 1 1 3

scillation period 12 gate delays

data path latency 6 gate delays 3 oscillations 35 cells 19-21 signal transitions link

1 1

00 01 10 11 00 01 10 11

1

2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2

link closure closure link

1 S CO 1

half-adder half-adder

closure

1 1

00 01 10 11

OR 3 3 3 3 1

links

1 2 2 2 2 2 2 1 1

1 1 B A 1 CI

closure closure closure

scillation period 18 gate delays

data path latency 6 gate delays 1 oscillation 24 cells 10-12 signal transitions

Other combinational ranks can be made a link Page 9

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1 1

00 01 10 11 00 01 10 11

1

2 3 3 3 3 3 3 3 3 1 1 1 1 1 1 2 2

link closure link

1 S CO 1

half-adder half-adder

closure

1 1

00 01 10 11

OR 3 3 3 3 1 1 2 2 2 2 2 2 1 1

links

1 1 B A 1 CI

closure closure closure

1 2 2

link

1 1 3 1 2 2 1 1 3

scillation period 12 gate delays

data path latency 6 gate delays 3 oscillations 35 cells 19-21 signal transitions link

1 1

00 01 10 11 00 01 10 11

1

2 3 3 3 3 3 3 3 3 2

1 S CO 1

half-adder half-adder

00 01 10 11

OR 3 3 3 3

finest oscillation granularity

1 2 2 1 1 1 2 2 1 1

scillation period 8 gate delays

data path latency 6 gate delays 6 oscillations 50 cells 30 signal transitions

1 1 2 2 2 1 3 4 1 2 2 3 4 2 1 2 2 1 2 2 2 4 3

1 1 B A 1 CI

closure closure closure

3 1 2 2 2 2 2 2 1 1

Any combinational rank can be made a link Page 10

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1 1

00 01 10 11 00 01 10 11

1

3 3 3 3 3 3 3 3 2

1 S CO 1

half-adder half-adder

00 01 10 11

OR 3 3 3 3 1 2 2 2 2 2 2 1 1

1 1 B A 1 CI

closure closure closure

finest oscillation granularity

ptimized

1 2 2 1 2 2

scillation period 6 gate delays

data path latency 6 gate delays 6 oscillations 34 cells 26 signal transitions

1 1 2 2 2 1 3 4 1 2 2 3 4 2 1 2 2 1 2 2 4 3 3 buf buf buf buf buf 1 1 2 28 buf thcomp 1 1 2 28 thcomp 1 1 2 28 thcomp 1 2 2 buf

Each destination closes with all its sources Each source is closed by all its destinations Each link is both destination and source

1 1

00 01 10 11 00 01 10 11

1

2 3 3 3 3 3 3 3 3 2

1 S CO 1

half-adder half-adder

00 01 10 11

OR 3 3 3 3 1 2 2 1 1 1 2 2 1 1

scillation period 8 gate delays

data path latency 6 gate delays 6 oscillations 50 cells 30 signal transitions

1 1 2 2 2 1 3 4 1 2 2 3 4 2 1 2 2 1 2 2 2 4 3

1 1 B A 1 CI

closure closure closure

3 1 2 2 2 2 2 2 1 1

The oscillation structure can be optimized in terms of the logic

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1 1

00 01 10 11 00 01 10 11

1

2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2

link closure closure link

1 2 2 2 2 2 2 1 1

links

1 1 B A 1 CI 1 S CO 1

closure

1 1

00 01 10 11

2 2 2 2 1

closure closure closure

half-adder half-adder OR

scillation period 20 gate delays

data path latency 7 gate delays 1 oscillation 26 cells 11-13 signal transitions

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1 1

00 01 10 11 00 01 10 11

1

3 3 3 3 3 3 3 3 2

1 S CO 1

half-adder half-adder

00 01 10 11

OR 3 3 3 3 1 2 2 2 2 2 2 1 1

1 1 B A 1 CI

closure closure closure

finest oscillation granularity

ptimized

1 2 2 1 2 2

scillation period 6 gate delays

data path latency 6 gate delays 6 oscillations 34 cells 26 signal transitions

1 1 2 2 2 1 3 4 1 2 2 3 4 2 1 2 2 1 2 2 4 3 3 buf buf buf buf buf 1 1 2 28 buf thcomp 1 1 2 28 thcomp

coarsest oscillation granularity unoptimized

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