Combinational Logic M. Sachdev, Dept. of Electrical & Computer - - PDF document

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Combinational Logic M. Sachdev, Dept. of Electrical & Computer - - PDF document

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ECE 223 Digital Circuits and Systems Combinational Logic M. Sachdev, Dept. of Electrical & Computer Engineering University of Waterloo 1 Combinational Circuits consists of logic gates with outputs that are determined entirely by the

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Combinational Logic

  • M. Sachdev,
  • Dept. of Electrical & Computer Engineering

University of Waterloo

ECE 223 Digital Circuits and Systems

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Combinational Circuits

consists of logic gates with outputs that are determined

entirely by the present value of the inputs (no memory)

Combinatorial circuits might be 2-level logic (SOP,POS) or multi-

level

Two important procedure

Analysis

– Given circuit schematic, explain its behavior

Design

– Given the specifications, build it

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Analysis Procedure

1.

Label all logic gate outputs and primary inputs

2.

Starting from primary inputs, represent outputs in terms

  • f their input variables

3.

Repeat 2, till you reach output

4.

Represent primary output(s) in terms of primary inputs

F2 = AB +AC +BC T1 = A +B +C T2 = ABC T3 = F2’T1 F1 = T2 +T3 Simplify the F1

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Design Procedure

1.

From Specifications, determine the required number of inputs and outputs

2.

Assign a variable to each input and output

3.

Derive a truth Table that defines the required relationship between inputs and outputs

4.

Perform logic minimization

5.

Draw the logic diagram

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Design Procedure - Example

  • Given input bits in BCD, design a circuit to convert

inputs to Excess-3 code outputs

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Output Excess-3 Code Input BCD z y x w D C B A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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Example – K maps

z = D’ y = CD +C’D’ = CD + (C +D)’ x = B’C +B’D +BC’D’ = B’(C +D) +B(C +D)’ w = A +BC +BD = A +B(C+D)

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Example – Schematic

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Binary Adder

  • Adder is an important component in many logic

circuits

  • Half Adder

(CS)2 = x plus y S = x’y +xy’ = x⊕y C = xy

S C y x 1 1 1 1 1 1 1

x y C S HA

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Full Adder

1 1 1 1 C 1 1 1 1 1 1 1 1 S z y x 1 1 1 1 1 1 1 1

(CS)2 = x plus y plus z

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Full Adder – K Maps & Schematics

1 01 00 1 1 yz x 1 1 11 10

S x x y y z z x´ y x x x´ y´ y´ y z z´ z´

01 00 1 1 yz x 1 1 1 11 10

S = x’y’z +x’yz’ + xy’z’ + xyz = x⊕y⊕z C = xy +xz +yz

S C

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Implementation with 2 Half Adders

x y z S C FA c2 y x HA z C HA s1 c1

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Half Subtractor

  • Produces x -y
  • D – difference
  • B – Borrow

D B y x 1 1 1 1 1 1 1

x y B D HS

D = x’y +xy’ = S of half adder B = x’y

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Full Subtractor

1 1 1 1 B 1 1 1 1 1 1 1 1 D z y x 1 1 1 1 1 1 1 1

(x -y) –z; where z represents a borrow D = x’y’z +x’yz’ + xy’z’ + xyz = x⊕y⊕z = S of full adder B = x’y +x’z +yz (same as C of full adder except x is inverted

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Parallel Adder

  • Often, we must add 2 n bit numbers and carry
  • Classical approach
  • (2n + 1) inputs and (n+1) outputs
  • Design a (n+1) output, 2-level (e.g. SOP) design
  • Problems
  • Too many gates
  • Fan-in is too large
  • Not practical for n>3
  • Use iterative circuit, reduced complexity
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Parallel Adder – 4 Bit Adder

  • For n = 4
  • Inputs

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  • Outputs

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  • Power, Gnd

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  • A 4 bit adder is accommodated in 16 pin package (MSI)

b0 a0 b1 b2 bn-1 a1 a2 an-1 s0 s1 s2 sn-1 c1 c2 c3 cn-1 cn . . . FA FA FA FA c0

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Parallel Adder - Issues

  • Fewer gates than 2-level implementation, however

significantly slower Rippling effect of carry

  • For an n bit adder
  • Propagation delay = (2xAverage gate delay)x(number of bits)
  • = 2nxd, where d = Average gate delay

ai ci si bi

  • Ci+1
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Carry Lookahead Logic

  • Define:
  • Carry Propagate

Pi = ai ⊕ bi for I = 0, ---- n-1

  • Carry Generate

Gi = ai bi

  • Now

si = ai ⊕ bi ⊕ ci = Pi ⊕ ci ci+1 = ai bi + ai ci + bi ci = ai bi + ai bi´ci + ai´bi ci = Gi + ci Pi

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Carry Lookahead Logic

  • Observation
  • All carries can be generated simultaneously

c2 = G1 + P1c1 c3 = G2 + P2c2 = G2 + P2G1 + P2P1c1 c4 = G3 + P3c3 = G3 + P3G2 + P3P2 G1 +P3 P2P1c1

  • Delay
  • P, G 2 gate delay
  • c

2 gate delay (2-level circuit)

  • S

XOR (2-level circuit)

  • 6 gate delays; independent of n
  • Practically, n is limited by # of connections and gate loading
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Carry Lookahead Logic

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4 Bit Adder Subtractor

  • Desirable to use same hardware for both operations
  • 2’s complement addition for subtraction
  • Overflow
  • Addition/subtraction of 2 n bit numbers may produce n+1 bit output
  • Problem if fixed # of bits (n) are allocated for input and output
  • Must detect its occurrence
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BCD Adder

1 1 1 1 1 1 S2 1 1 1 1 1 1 1 1 S1 k Binary Sum # BCD Sum 11 1 1 1 1 13 1 1 1 1 9 1 1 1 10 1 1 1 12 1 1 1 14 1 1 1 1 1 5 1 1 1 6 1 1 1 7 1 1 1 1 8 1 1 4 1 1 1 S4 S8 C Z1 Z2 Z3 Z8 1 1 1 1 1 1 1 1 1 1 1 1 15 1 3 2 1

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1 1 S2 1 1 S1 1 1 1 1 k Binary Sum # BCD Sum S4 S8 C Z1 Z2 Z3 Z8 1 1 1 1 1 1 1 1 1 1 1 1 19 18 17 16

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Magnitude Comparator

  • Classical approach
  • 3 outputs and 2n inputs
  • Large logic complexity, if n >3
  • Alternative Approach
  • 2-step process

F1 (A = B) F2 (A > B) F3 (A < B) magnitude comparator 4 4 A B ≡ ≡ ≡

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Magnitude Comparator

  • 2-step process

1.

Define

xi ≡ ( Ai Bi ) = Ai Bi + Ai´Bi´ , 0 < i < 3

2.

F1 = ( A = B) = x3x2x1x0

F2 = ( A > B) = ( A3 > B3 ) + (A3 = B3 ) • (A2 > B2 ) + (A3 = B3 ) • (A2 = B2 ) • (A1 > B1 ) + (A3 = B3 ) • (A2 = B2 ) • (A1 = B1 ) • (A0 > B0 ) = A3 B´3 + x3 A2B´2 + x3x2 A1B´1 + x3 x2x1 A0B´0 F3 = A´3 B3 + x3 A´2B2 + x3x2 A´1B1 + x3 x2x1 A´0B0 = ( F1 + F2 )´

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Magnitude Comparator

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Decoders

  • Code of n bits can represent 2n decode outputs
  • One output is true at a time

x y x y x´ x y x´ y´ y´ y´ x´ x y

  • 1

D1 1 D2 1 1 D3 D0 y x 1 1

= D0 = D1 = D2 = D3

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Decoders with Enable

  • If E = 0 all outputs are disabled
  • Outputs are active low

1 E 1 1 1 1 X X 1 1 1 Y1 1 1 1 Y2 1 1 Y3 Y0 y x 1 1 1 1 1 1

Y0 Y1 Y2 Y3 E

  • x

y

  • Y0

Y1 E y x Y2 Y3 21 2 x 4 20 decoder (enable)

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Larger Decoders

  • Larger decoders are built with smaller ones
  • Special decoders (other than n to 2n)
  • BCD to 7 segment display
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Function implementation using Decoders

  • Adder S = ∑(1,2,4,7); C = ∑(3,5,6,7)

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Encoders

  • Does reverse operation to decoder
  • Constraint – only one input is active at a time
  • Example, Octal to Binary Encoder

Z = D1 +D3 +D5 +D7; y = D2 +D3 +D6 +D7; x = D4 +D5 +D6 +D7

1 1 1 1 x Outputs 1 1 1 1 y 1 D0 Inputs 1 1 1 1 1 1 1 1 1 1 D3 D4 D5 1 D1 1 D2 1 1 1 D6 D7 1 z

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Priority Encoders

  • Encoder with priority function
  • Multiple inputs may be true simultaneously
  • Higher priority input gets the precedence

1 1 1 X X Outputs Inputs X X 1 D0 1 X x 1 1 X y 1 X X V D3 D2 D1 1 1 1

  • Valid bit, V, indicates two inputs are true at the

same time

  • Higher priority input gets the precedence

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Priority Encoders - Circuit

x = D2 +D3 y = D3 +D1D2’ V = D0 +D1 +D2 +D3

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Multiplexers

  • A Multiplexer has n inputs, one output, and S

(2s = n) select (control) inputs

Passes (selects) an input depending on S

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Function Implementation with Multiplexers

  • Let F(x,y,z) = ∑(1,2,6,7)
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Multiplexers with Tri-stated Gates

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Book Sections – Combination Circuits

Material is covered in Sections 4.1 – 4.5, 4.7 – 4.10