Combinatorial networks- II Digital Systems M 1 Adder Lets see the - - PowerPoint PPT Presentation

Combinatorial networks- II

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Digital Systems M

Adder

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• Let’s see the truth table of a combinatorial network whose output values correspond to the

numerical values of a 2-bit adder (Half Adder) ab Sum Carry 00 0 0 01 1 0 Sum = a ⊕ b = a exor b 10 1 0 11 0 1 Carry=ab Sum Carry a b

HA

b a Sum Carry

• Let’s see the truth table of a combinatorial network whose output values correspond to the

numerical values of a 3-bit adder (Full Adder). Canonical synthesis SP abc Sum Carry 000 0 0 001 1 0 010 1 0 011 0 1 100 1 0 101 0 1 110 0 1 111 1 1 C= !abc+a!bc+ab!c+abc = !abc+a!bc+ab!c+abc+abc+abc = ab(c+!c) + ac(b+!b) + bc(a+!a) = ab + ac + bc For the carry we have also

Added terms (idempotence)

(It could have been intuitively deduced since two 1’s are enough for generating a carry !!!)

HA

b a

Sum1 = a exor b

Carry1=ab

c Sum

Carry2=c(a exor b)

Carry Full Adder

Sum2 =a exor (b exor c)

HA

Sum = !a!bc+!ab!c+a!b!c+abc=!a(!bc+b!c)+a(!b!c+bc) =!a(b exor c)+a!(b exor c) = a exor (b exor c) Carry = !abc+a!bc+ab!c+abc = c(a exor b) + ab(c+!c) = c(a exor b) + ab

Adder

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HA

a0 S0 C b0

To add a binary number of n bit, n-1 FA e 1 HA must be used

FA

a1 S1 C b1

FA

a2 S2 C b2 NB: Normally the integrated circuits provide 4 bit FAs. With this network a new logical level (delay) is introduced for each couple of bit to be added. It must be remembered however that this is a combinatorial network which corresponds to a truth table which can be always

synthesised as a two levels

network (minimum delay). In the 4 bit integrated FAs the carry is always generated with a two level network in order to accelerate the operations of the next level FA.

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FA 4-bit 74X283

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FA 8-bit

Carry Look Ahead I

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• With 4 bit full-adders a fast carry generator is implemented

Two level network (SP) Remember: a combinatorial network can be always implemented as a two level PS od SP

• Considering the sum of two binary numbers with Ai and Bi the bits in the i-th position we define Gi

the logical product Ai*Bi (1 only if both bit are 1) and Pi the logical sum Ai or Bi which if Ai =1 or Bi=1 produces arithmetically always a carry (Ci+1) if there is a carry (Ci of index i)

• Two carries are defined: carry generate (G) and carry propagate (P)
• It follows that

Ci+1=(Gi or PiCi ) (Gi =1 if Ai=Bi=1; PiCi =1 if A ior Bi=1 and Ci =1) (if Gi =1 then PiCi has no infuence. If Gi =0 and Pi=1 then PiCi =Ci since a carry is produced if there is a carry from the precious stage and one element of the addition is 1). Therefore we have (here symbols + indicate always or) C1=G0+P0C0 C2=G1+P1C1 = G1 + P1(G0+P0C0)= G1 + G0P1 + C0P0P1 etc. and then substituting C4= G3+G2P3+G1P2P3+G0P1P2P3+C0P0P1P2P3 (carry of the 40h bit)

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Carry Look Ahead II

A combinatorial 4-bit Carry Look Ahead generator produces two signals CG3 e CP3 (Full Adder number 3 indexes) Carry Generate4 CG3= G3+G2P3+G1P2P3+G0P1P2P3 Carry Propagate4 CP3=P0P1P2P3 C4= G3+G2P3+G1P2P3+G0P1P2P3+C0P0P1P2P3 (see previous slide)

• In order to generate C5

C5= G4 + P4C4 = G4 + P4(G3+G2P3+G1P2P3+G0P1P2P3+C0P0P1P2P3) = G4 + P4CG3 + P4CP3C0

where CG3 and CP3 are generated by the preceding four FAs. Normally CGi the CPi and the Ci of several cascaded Full Adders are inserted in a combinatorial circuit which allows to speed up the operations. There are ohter methodologies for the Carry Look Ahead generation NB In the english texts very often CP is indicated as PG and CG as GG Two level expression(SP)

A4*B4 A4+B4

Full adder for adding n-bit

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4-bit Full Adder B0 B1 B2 B3 A0 A1 A2 A3 C0 C4 4-bit Full Adder B4 B5 B6 B7 A4 A5 A6 A7 C8

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http://ee.usc.edu/ee459lib/datasheets/DM74LS181.pdf

Arithmetic Logic Unit

Multifunction Circuit (including a 4-bit FA)

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Positive true logic (active high) : «1» the highest electrical potential and «0» the lowest Negative true logic (actie low): the reverse

74LS181

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S3 S2 S1 S0

Mode=1

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!A A A plus 1 1 !(A+B) A+B (A+B)plus 1 1 !AB A+!B (A+!B)plus 1 1 1 0000 Minus 1 zero 1 !(AB) A plus A!B (A+A!B)+1 1 1 !B (A+B) plus A!B (A+B )plus A!B plus 1 1 1 AxorB Aminus B minus 1 A minus B 1 1 1 A!B A!Bminus 1 A!B 1 !A+B A plus AB A plus Abplus 1 1 1 !(AxorB) AplusB Aplus Bplus 1 1 1 B (A+!B)plusAB (A+!B) plus AB plus 1 1 1 1 AB AB minus 1 AB 1 1 1111 AplusA A plus Aplus 1 1 1 1 Aor!B (A+B)plusA (A+B)plusAplus 1 1 1 1 AorB (A+!B)plusA (A+!B)plusAplus 1 1 1 1 1 A Aminus 1 A

Mode=0

Cin=1 Cin=0 Numeric addition Numerical subtraction

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• M=1 all internal carries are inhibited and the device implements the table logical

functions

74LS181

Carry_In Carry_Out Comparison 1 1 A≤B 1 A>B 1 A<B A≥B

• M=0 internal carries are enabled and the device

implements the table arithmetic functions

• Three carries:
• Ripple Carry (Carry_Out = C4), the «normal» arithmetic carry
• Two carry look-ahead carries : carry propagate (CP3) and carry generate (CG3)
• An output is available for AeqB (A equal B) open collector for wired AND. The equal

is meaningful when S = 0110 with Mode=0 and Carry_in=1.

• If S=0110 the Carry_Out can be used for the comparison of two absolute value

numbers A and B

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Carry_In Mode A(3:0) B(3:0) S(3:0) AeqB Carry Propagate (CP3) Carry Generate(CG3) Carry_Out (C4) Output(3:0)

15 N.B. Note 1 indicates that the datum is right shifted one position (multiply by 2) Logical sum Numeric addition Numerical subtraction

z z z z z z z z z z z z z z z z z z z z z z z z z

See next slide

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N.B. Here we consider ONLY the High and Low signal values. The logical intepretation is different if the logic is either positive or negative true S(3:0)=LHHH M=H Positive true Negative true Logic Logic AiBi Zi AiBi Zip AiBi Zin L L L 0 0 0 1 1 1 L H L 0 1 0 1 0 1 H L H 1 0 1 0 1 0 H H L 1 1 0 0 0 1 Zipos = Ai!Bi Zineg = Ai+!Ai!Bi=Ai+!Bi Example

Circuit electrical potential

17 Extreme values

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Multiplexer (MUX)

• Two ways multiplexer: one of the two inputs is selected according to value of the

control signal (C).

• The truth table and the canonical function of a MUX with four inputs and two control

signals C1 e C2 ?

z y x C

Z = CY + !CX

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Mux_8_to_1

Bus Input0-7 Bus - selection X0-2

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DEMULTPLEXER (DEMUX or decoder)

A C Z1 = !CA Z2 = CA

• The truth table and the canonical function of a DEMUX with four outputs and two

control signals C1 e C2 ?

• This circuit is called also

DECODER because if in n-way demux the input a is at logical value 1, only one output is at logical value 1, that corresponding to one of the 2n control input binary configurations (only one in this figure – c). Obviously if no input is 1 all outputs a 0 no matter what the values of the control inputsis. The circuit therefore “decodes” the input binary value (that is corresponds to the control signals binary value)

• Two ways demultiplexer: the input logical value is redirected to one of the two
• utputs (Z1 e Z2) according to value of the control signal (C).

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Example Y2N = !((!AB!C)G1!G2AN!G2BN)

Decoder 3:8. Control inputs are A,B and C the output YiN [corresponding to the binary value (i) of ABC (C=> 22, B=>21, A=>20)] is 0 (Low) only if enable inputs G1=H and G2AN=G2BN=L otherwise all outputs are H.

23 Bus Output0-7

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74686 comparator



This 8 bit comparator is a combinatorial network whose inputs are two binary 8 bit numbers (absolute value). It checks whether they are identical and/or whether one is greater (or lower) than the other. It has two negative true inputs G1N e G2N which enable the two sections of the

• network. G1N enables to check whether the two numbers are identical while G2N enables the

greater/lower section.



The first section consists of XNORs of all bits with the same index (i.e. P0 and Q0). A XNOR is 1 if the bit are identical. The 8 outputs are NANDed with G1N: its output PEQN is 0, negative true , if all XNOR bis are 1.



The second section is made of 8 ANDs with increasing number of inputs: they compare the bit starting from the most significant…. Analyze the network

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Outputs negative true

Minimum cost networks

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• The“cost” (which in this context means “complexity”) has no unique meaning and depends on

many factors

• In our context the minimum cost refers to the minimum number of devices needed to

implement a two levels combinatorial logical function. Notice that there can be more than one minimum cost implementations

• Minimum expression: an expression which corresponds to the minimum cost implementation
• Normal expression: an SP (or PS) expression. Two levels. The

canonical expressions are normal but they are not the only normal expressions

• Non-redundant expression: a normal expression SP (or PS) whose terms are all necessary.

Examples

• Example 1 F= ab+bc+ad: no product can be removed without modifying the truth table .
• Example 2 F=b!c+ac. Expression b!c+ab+ac (which corresponds to the same truth table)

wouldn’t be non-redundant since term ab could be removed without altering the truth table

• A minimum cost network in our case is a normal non-redundant expression
• In the following slides we use only SP for sake of simplicity (being the extension to the

PS straightforward– duality)

Minimum cost networks

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• Implicant: a product term of n or less input variables which is 1 only for

input combinations where the function is not 0

• Example F= abc + ac + cd + ad (all products are implicant)
• Prime implicant: an implicant which is not an implicant any more if a

letter is removed

• Example F= ac + cd (both products are prime implicants)
• Essential prime implicant: an implicant which is the only one having value

1 for some input configurations where the function must be 1 (that is there are no other prime implicants which cover one ore more «1s» of the function)

• Example F= abc + ac + cd (abc is not essential)
• It follows that a minimum cost network is an non-redundant sum of

essential prime implicants (only those strictly necessary)

Karnaugh maps

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Bi-dimensional representation of the truth table of a function of 2,3,4,5 and 6 variables, whose values are indicated on the border of the maps so that two adjacent input configurations (differing for one single bit) are topologically adjacent. Obviously the number of the map squares is a power

• f two (all possible input combinations)

1 1 a b 1 1 1 00 01 11 10 1 a bc 1 1 1 1 00 01 11 10 00 01 11 10 ab cd 1 1 1 1 1 1 1 1 00 01 11 10 00 01 11 10 ab cd 1 1 1 1 1 1 1 00 01 11 10 00 01 11 10 ab cd 1 1 1 1 1 1 1 1

e=0 e=1

To be considered vertically

• verlapped

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Karnaugh maps

• The Karnaugh maps can be easily used to underline the adjacences
• f

the input configurations where the function is «1» allowing to graphically implement the algebra theorems (i.e. ab + a!b = a)

00 01 11 10 00 01 11 10 ab cd

adjacent adjacent adjacent

• The input adjacence in the Karnaugh maps must be interpreted in

spherical sense. In the following example the square a=0, b=0, c=0 and d=1 is adjacent to square a=1, b=0, c=0, d=1 (green) as it is the case for 0001 and 0011. The grahical representation allows to easily detect the input confgurations which differ for a single bit

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Karnaugh maps

Let’s consider the truth table of a three inputs function

abc F 000 1 001 1 010 1 011 0 100 1 101 0 110 0 111 1

= !a!b!c+!a!bc+!ab!c+a!b!c+abc = !a!b!c+!a!b!c+!a!b!c+!a!bc+!ab!c+a!b!c+abc = = !a!b+!b!c+!a!c+abc (much simpler)

• What was exploited ? The adiacences of the product terms of the canonical
• expression. But the same can be found it in a Karnaugh map!!! And the same
• perations executed using the algebra theorems can be derived by analyzing the

adjacents groups. The greatest rectangular groups of «ones» must be found (a rectangular group is a group of 2n squares each one having n adjacent squares) which cannot be enlarged without including zeroes. The product terms (implicants) of minimum complexity (prime implicants) can be obtained observing the input variables which do not change withing the group (taken as true if present with value 1 and viceversa) . Spherical adjacences!! Coverture: each “one” of the function must be covered at least by one group (but also by more than one group – idempotence)

F= + abc !a!b

!a!b!c+!a!bc

+ !b!c

!a!b!c+a!b!c

Idempotence

00 01 11 10 1 a bc 1 1 1 1 1

Mintermin alone !

+ !a!c

!a!b!c+!ab!c

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Karnaugh maps

00 01 11 10 1 a bc 1 1 1 1 1 1

F1= !b+ac+!a!c

00 01 11 10 00 01 11 10 ab cd 1 1 1 1 1 1 1 1

Here we have no adjacent minterms => canonical synthesis !!!

00 01 11 10 00 01 11 10 ab cd 1 1 1

1

1 1 1 1 1 1 1

1 F3= !a!b!cd+!a!bc!d+!ab!c!d+!abcd+ab!cd+abc!d+a!b!c!d+a!bcd All product terms are prime implicants and are essential too since they cover «ones» not covered by

• ther

prime implicants !b!d + !bc + !ad + !a!c + b!cd + F2= ac!d The implicant !a!b (dashed) would be prime but it is not essential

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Karnaugh maps

00 01 11 10 00 01 11 10 ab cd 1 1 1 1 1 1 1 1 1 00 01 11 10 00 01 11 10 ab cd 1 1 1 1 1 1 1 1 1

1 e=0 e=1 The two 4 bits maps differ for the 5-th variable (e) and can be interpreted as two spherical surfaces having the same center F= !b!d + !a!c!e + a!bc +ade + ac!d + bcde

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00 01 11 10 00 01 11 10 ab cd 1 1 1 1 1 1 1 1 1 00 01 11 10 00 01 11 10 ab cd 1 1 1 1 1 1 1 1 1

1 e=0 e=1

F= In this case the prime rectangular groups of «zeros» must be found (prime implicated). The sum terms of minimum complexity can be derived by the squares variables which do not change, taken as negate if 1 and viceversa

PS Synthesis

(!a+c+!d+e)(!a+!b+c+d)(!a+!b+!d+e) (a+!b+!c+e)(a+b+!c+!d)(a+c+!d+!e)(a+!b+d+!e)

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00 01 11 10 00 01 11 10 ab cd 1

1

1 1 1 1 1 1

1

Karnaugh maps

!b!d + bd + !a!bc F=

00 01 11 10 00 01 11 10 ab cd 1

1

1 1 1 1 1 1

1 !b!d + F= bd + !acd The two synthesized functions are equivalent, of the same complexity and both consisting of prime implicants. This can occur very often

General rule: in the maps detect first the ones (zeros) which are covered by only one implicant (implicated) and use the corresponding rectangular group (essential). The the other ones (zeros) must be covered. There are however cases (as that of the figure) where there are no ones (zeros) covered by a single prime essential implicant (implicated)

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Karnaugh maps

• Combinatorial neworks not fully specified:

for some input combinations the outputs are not defined (normally this is the case of impossible input combinations:i.e. 7 segments where the only input values are 0 to 9).

00 01 11 10 00 01 11 10 ab cd 1 1 1 1 1 1 1 1 1 1 1 1 1

The table which has been actually synthesized

00 01 11 10 00 01 11 10 ab cd 1 1 1 x 1 x 1 1 1 1 x 1 1 1

F=!b + a+ !c!d

X => 1 X => 0

• In this case the function in the map can be «don’t care» (normally indicated by x or - )

and the value can be used as “one” and “zero” in order to obtain implicants (implicated) of minimum complexity. The don’t cares can be in turn interpreted as zero

• r one according to the needs

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fe = A + !BC

00 01 11 10 00 01 11 10 ab cd 1 1 1 1 1 1 1 1 1 1

Seven segments

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Design with the Karnaugh maps

• starting from the truth table - a

packed BCD to binary converter when the max value

• f

the packed BCD code is 1 1001 (19) and the even numbers must not be converted (packed BCD => Binary for odd numbers). What are the don’t cares? BCD | Binary

• ------|----------

ε δχβα | edcba 0 0001 | 00001 0 0011 | 00011 0 0101 | 00101 0 0111 | 00111 0 1001 | 01001 1 0001 | 01011 1 0011 | 01101 1 0101 | 01111 1 0111 | 10001 1 1001 | 10011 All other input configurations are don’t cares Input Output

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BCD | Binary

• ------|----------

ε δχβα | edcba 0 0001 | 00001 110 0 0011 | 00011 310 0 0101 | 00101 510 0 0111 | 00111 710 0 1001 | 01001 910 1 0001 | 01011 1110 1 0011 | 01101 1310 1 0101 | 01111 1510 1 0111 | 10001 1710 1 1001 | 10011 1910 b= !εβ ε!β +

00 01 11 10 00 01 11 10 δχ βα

• 1
• 1
• 00 01 11 10

00 01 11 10

δχ βα

• 1
• 1
• 1
• ε=0

ε=1 = ε ⊕ β Synthesize the other functions Packed BCD to binary for odd numbers (Let’s synthesize the b function)

1 1 1 1 1 1 1 1 00 01 11 10

X1 X2

00 01 11 10

X3x4 39

Z2 = x1x2 + x2x4 + !x3x4 Z1= x1x3 + x1x4 + x2x3 Can we derive the Karnaugh map from the SP (PS) expressions ?

1 1 1 1 1 1 1 1

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6 variables Karnaugh maps

ba 00 01 11 10 00 01 11 10 dc ba

1

• 1
• 00 01 11 10

00 01 11 10

dc

1 1

• 1

1

• 1
• ez=00

ez=01

00 01 11 10 00 01 11 10 dc ba

1

• 1
• 00 01 11 10

00 01 11 10

dc ba

1

• 1
• 1
• ez=10

ez=11 F = !a!b!c!z + bc + a!b!cz + !a!ez F = (b+!a+z) (!b+c+z) (!b+!a+c+!z)(b+!c)(a+!e+!z) And for more variables?

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Quine – McCluskey method (I)

• Two steps procedure
• Prime implicants identification
• Minimum set covering the function detection
• Table (algorithmic) method
• No limit for the variables number
• Software synthesizable
• Easy «don’t» care handling
• Grouped minterms
• Each group includes minterms with

the same number of variables either true or complemented

• The minterms are listed numerically

within the groups

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Metodo di Quine – McCluskey (II)

Example => f (A,B,C,D)= Σm(4,5,6,8,9,10,13) with don’t care Σi(0,7,15) (Σ is the logic sum - 4 => 0100, 13 => 1101 etc.) (In the following example the minterms are represented with the numerical value corresponding to each input variables configuration)

• 1-1 (g&n,h&m) β
• The the terms of column II are «combined» again in the

following column (III) (if possible) provided they have the don’t care in the same position and differ b a single «one» (they can produce – by couples – the same result). The don’t care are not recombined otherwise we would go back to square one.(i.e. by recombining a and b we wouldo btain 0000 !!) The aim of the combinations is to obtain in steps increasingly simpler implicants until prime implicants are produced

01-- (c&i,d&g) α * * ^ ^ ^ ^ * * ^ * ^ ^

• Al groups with * are prime implicants (which cannot be

recombined)

* *

• The process is repeated until no more combinations

are possible. ABCD

• Minterms grouping in the first column (in red the don’t

cares) according to the number of «ones» and «zeros». Successive groups differ for a single «one»

0000 (0) 0100 (4) 1000 (8) 0101 (5) 0110 (6) 1001 (9) 1010 (10) 0111 (7) 1101 (13) 1111 (15) 0 «ones» 1 «one» and 3 «zeros» 2 «ones» and 2 «zeros»

• Comparison in the column I between the elements with N

«ones» and those with N+1 «ones» and their combination in

• rder to
• btain

less complex terms (column II). The combination corresponds to the use of the property a!b + ab= a(!b + b)=a. Synbol ^ if combined, * if not.

0-00 (0 & 4) a ^ ^ ^

I column II columns III column

• 000 (0 & 8) b

010- (4 & 5) c 01-0 (4 & 6) d 100- (8 & 9) e 10-0 (8 & 10) f 01-1 (5 & 7) g

• 101 (5 & 13) h

011- (6 & 7) i 1-01 (9 & 13) l

• 111 (7 & 15) m

11-1 (13 & 15) n ^ ^ ^ ^ ^ ^ ^ ^

Combination (don’t care x in the same position) N.B.g can be combined with two different terms (4&5&6&7) (5&7&13&15)

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Metodo di Quine – McCluskey (III) method

Coverture table (minterms columns – prime implicants rows) Obviously ONLY the real minterms must be covered, NOT the don’t care

NB If a column has a single X the corresponding prime implicant is obviously essential

a 0,4(0-00) b 0,8(-000) e 8,9(100-) f 8,10(10-0) l 9,13(1-01) α 4,5,6,7(01--) β 5,7,13,15(-1-1) 4 X X 5 X X 6 X 8 X X X 9 X X 10 X 13 X X

f (A,B,C,D)= Σm(4,5,6,8,9,10,13)

On the left all found prime implicants and in the columns the function minterms to be synthesized: X indicate which prime implicants covers which minterms of the functon

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Quine – McCluskey (IV) method f = A!B!D + A!CD + !AB f l α

http://en.literateprograms.org/Quine-McCluskey_algorithm_%28Java%29 http://www.mathcs.bethel.edu/~gossett/DiscreteMathWithProof/QuineMcCluskey.html

0,4(0-00) 0,8(\000) 8,9(100-) 8,10(10-0) 9,13(1-01) 4,5,6,7(01--) 5,7,13,15(-1-1) 9 X X 13 X X

Then we search for the minimum set covering 9 and 13 The already covered columns are removed Columns 4,5 and 8 are automatically covered by essential prime implicants (see previous slide)

0,4(0-00) 0,8(-000) 8,9(100-) 8,10(10-0) 9,13(1-01) 4,5,6,7(01--) 5,7,13,15(-1-1) 4 X X 5 X X 8 X X X 9 X X 13 X X

Essential

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Integrated BCD adder

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47

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NAND (NOR) circuits

• Although the elementary logic operators (AND, OR, NOT) are available as IC or FPGA etc. it

can be useful sometimes to use only one type of operator: NAND or NOR X Z X y Z X y Z Z X y 1 Z X 1

Any two levels SP (PS) circuit can be implemented using only NANDs (NORs). Example: SP two-ways multiplexer.

1 X Y 1 Z

( De Morgan)!!

z a b c a z b c 1 z = = a!c + bc = ![(!(a!c) !(bc)] (De Morgan)

3-state drivers OE I OE=1 I U U OE=0 I U I OE U OE I 1 1 1 1 U 1 Z Z

Voltage ?

?

OE=0 1 U=?

U value ? What must be granted in this network ? When U has a meaningful logical value ?

1 U=? OE1 OE2 I1 I2

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Common bus circuits

• Very often (and in particular in microprocessors based systems) many devices

must drive– in different times - the same wire (in case of many devices with multiple wires the name used is bus) and multiplexers (for instance with many inputs – say 30 or 40) can’t be practical because of the circuit complexity. High impedance X C Y 1 1 1 1

• Z

1 Z

X Y C=1 X Y C=0

In case of C=0, Y wire is open, not connected to any voltage !!!!!!!!! The high impedance is NOT a logic state and does NOT propagate

Y

Y is not in high impedance status but the

• utput of the second inverter takes the

value deriving from an unconnected input (which in general is interpreted as a «dirty» high level )

Y

• In this case devices with

tri-state outputs are used that is devices whose

• utputs can be enabled (and in this case the output follows the logic of the

circuit) or disabled (and in this case the circuit output is electrically disconnected from output connected to output pin). Typically tri-state circuits are buffer

1

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244

1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 EN1* EN2*

74XX244 ENx* (negative true) xAi xYi

8 bit 3-state driver (2 groups of 4 bit)

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54

55

EN* Bi DIR Ai

A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 EN* DIR

74XX245

245

8 bit bidirectional driver (transceiver)

56

57

58

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Tristate based Mux

X0 C0 X1 C1 Xn Cn

Ci are decoded signals each one enabling one signal source. If the bus is made of multiple wires, Ci enables all outputs of the same source

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Eprom Memories

• An EPROM memory (Erasable Programmable Read Only Memory) is a device with n

binary inputs and 8 binary outputs. For each input combination of the 2n possible combinations (which can be considered therefore as minterms) it is possible to define and permanently store in the device eight binary values which correpond to the 8

• utputs.
• Each of the 8 outputs has value 0 or 1 for each of the 2n combinations of the inputs

and therefore the EPROM allows to synthesize in canonical form 8 functions on n variables

61

Eprom memories

1 1 1

D E C O D E R “0” “1” 2 n-1 1 m n Y0 Y1 Y7

where “n” is the minterm expressed as binary number (see Quine-McCluskey method) and Fj (n) is the function value for that minterm (0 or 1)

With an EPROM is therefore possible to synthesize in canonical form 8 (eight) combinatorial functions of n variables (j=0..7)

Yj =“0”Fj (0)+”1”Fj(1)+”2”Fj (2) +… “i”Fj (i)… “2n-1“Fj (2n-1) minterms

1

EPROM

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2n-1 m 3 2 1 a b c d f

W Z

2n-2

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EPROM memories

• Non volatile read-only memories
• Capacity: multiple of 2: 32K, 64K,

128K, 256K……

• Identification number: 27512, 271024 (the

indicate the number of Kbits)

VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND VCC PGM* NC A14 A13 A8 A9 A11 OE* A10 CE* D7 D6 D5 D4 D3

EPROM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

128K × 8 Ai CE* OE* Di Tce Tacc Toe CE* OE* Di Cell M/bit i

64

Implement through an EPROM a 6 bit Gray/Binary and Binary/Gray converter