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Chapter 1 Combinational Logic Process Control Ch 1- 1 Flaxer Eli - PDF document

Chapter 1 Combinational Logic Process Control Ch 1- 1 Flaxer Eli - Process Control Chapter Outline Documentation Standards for digital systems. Combinational Logic Design Structures : - Logic Gates - Decoders - Encoders -


  1. Chapter 1 Combinational Logic Process Control Ch 1- 1 Flaxer Eli - Process Control Chapter Outline • Documentation Standards for digital systems. • Combinational Logic Design Structures : - Logic Gates - Decoders - Encoders - Three-State Buffers - Multiplexers - Demultiplexers - Adders Ch 1- 2 Flaxer Eli - Process Control

  2. Basic logic Gates X X Z Z X Z Y Y NOT OR AND X Y Z X Y Z X Z 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 1 1 1 1 Ch 1- 3 Flaxer Eli - Process Control No Basic logic Gates X X Z Z Y Y NOR NAND X Y Z X Y Z 0 0 1 0 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 1 0 Ch 1- 4 Flaxer Eli - Process Control

  3. No Basic logic Gates X X Z Z Y Y NXOR XOR X Y Z X Y Z 0 0 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 1 1 Ch 1- 5 Flaxer Eli - Process Control Timing Diagrams • /ENABLE IN OUT Logic Circuit /ENABLE IN OUT t OUT • Delay depends on - Internal circuit structure /ENABLE - Logic Family type IN - Source Voltage - Temperature OUT t OUTmin t OUTmax Ch 1- 6 Flaxer Eli - Process Control

  4. Timing Diagram for Data signals (Bus) • /WRITE Logic IN OUT Circuit IN new data /WRITE (Memory) OUT old data new data • t1 : t setup t2 t4 t3 • t2 : t OUTmin • t3 : t OUTmax t1 • t4 : t hold Ch 1- 7 Flaxer Eli - Process Control Decoder • Multiple-input/multiple-output device. • Inputs ( n ) are less than outputs ( m ). input code output • Converts input code words into output code DECODER code words. • One-to-One mapping : enable - Each input code produces only one inputs output code. • Input codes : - Binary Code - Gray Code - BCD Code - Your Code ! Ch 1- 8 Flaxer Eli - Process Control

  5. Binary Decoder • n-to-2^n decoder : n inputs and 2^n outputs. • Input code : Binary Code. • Output code : 1-out-of-2^n , One output is asserted for each input code. • Example : n=2, 2-to-4 decoder • Inputs Outputs EN I 1 I 0 Y 3 Y 2 Y 1 Y 0 Y0 I0 0 x x 0 0 0 0 Y1 I1 1 0 0 0 0 0 1 Y2 1 0 1 0 0 1 0 EN Y3 1 1 0 0 1 0 0 1 1 1 1 0 0 0 Ch 1- 9 Flaxer Eli - Process Control Encoders • Multiple-input/multiple-output device. output • Perfoms the inverse function of a Decoder. input code code ENCODER • Outputs ( m ) are less than inputs ( n ). • Converts input code words into output code words. Ch 1- 10 Flaxer Eli - Process Control

  6. Binary Encoder • 2^n-to-n encoder : 2^n inputs and n outputs. Binary encoder • Input code : 1-out-of-2^n. I0 • Output code : Binary Code I1 • Example : n=3, 8-to-3 encoder I2 Y0 Inputs Outputs I3 Y1 I0 I1 I2 I3 I4 I5 I6 I7 Y0 Y1 Y2 I4 Y2 1 0 0 0 0 0 0 0 0 0 0 I5 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 I6 0 0 0 1 0 0 0 0 0 1 1 I7 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 Ch 1- 11 Flaxer Eli - Process Control Priority Encoder • 74x148 Inputs Outputs 74x148 /EI /I0 /I1 /I2 /I3 /I4 /I5 /I6 /I7 /A2 /A1 /A0 /GS /EO 1 x x x x x x x x 1 1 1 1 1 EI 0 x x x x x x x 0 0 0 0 0 1 I7 0 x x x x x x 0 1 0 0 1 0 1 0 x x x x x 0 1 1 0 1 0 0 1 I6 A2 0 x x x x 0 1 1 1 0 1 1 0 1 I5 A1 0 x x x 0 1 1 1 1 1 0 0 0 1 I4 A0 0 x x 0 1 1 1 1 1 1 0 1 0 1 I3 0 x 0 1 1 1 1 1 1 1 1 0 0 1 GS 0 0 1 1 1 1 1 1 1 1 1 1 0 1 I2 0 1 1 1 1 1 1 1 1 1 1 1 1 0 EO I1 I0 • /GS is asserted if any of the inputs is selected • /EO is asserted when no input is selected ( used for cascading encoders ) Ch 1- 12 Flaxer Eli - Process Control

  7. Three State Buffers/Drivers • A buffer/inverter with enable input Buffer Buffer Inverter Inverter Actice High Enable Actice Low Enable Active High Enable Actice Low Enable • The ouput is floating ( High Impedance, Hi-Z ) when the enable input is deasserted ( The input is isolated from the output ) • Application: Controlling the access of a single line/bus by multiple devices Ch 1- 13 Flaxer Eli - Process Control Multiplexers • Multiplexing : transmitting large number of signals over a small number of channels or lines • Digital multiplexer (MUX ) : selects one of many input lines and directs it to a single output. • Selection lines controls the selection of a particular input • n selction lines, 2^n inputs , single output. • Example : 4-to-1 line multiplexer : • Function Table : I0 S1 S0 Y 0 0 I0 I1 × 4 1 Inputs Output Y 0 1 I1 MUX I2 1 0 I2 I3 S1 S0 1 1 I3 Select Ch 1- 14 Flaxer Eli - Process Control

  8. Demultiplexers • Demultiplexer (DMUX) performs the opposite function of a MUX. • A digital Demultiplexer receives input data on a single input and transmits it on one of 2^n possible outputs according to the value of the n select inputs • MUX/DMUX are used in data transmission Source Destination A A B B BUS MUX DMUX C C Select Select Ch 1- 15 Flaxer Eli - Process Control 1-to-4 DMUX • 1-to-4 DEMUX Function Table IN S1 S0 D0 D1 D2 D3 D0 x 0 0 IN 0 0 0 D1 Input 1 × 4 Outputs x 0 1 0 IN 0 0 IN DMUX D2 x 1 0 0 0 IN 0 D3 x 1 1 0 0 0 IN S1 S0 Select Ch 1- 16 Flaxer Eli - Process Control

  9. Half Adder • Truth table : X Y S=(X+Y) CO X 0 0 0 0 S Y 0 1 1 0 1 0 1 0 CO 1 1 0 1 • = ⊕ S X Y = • CO X Y Ch 1- 17 Flaxer Eli - Process Control Full Adder • Truth Table X S X Y CIN S COUT Y 0 0 0 0 0 CIN 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 COUT 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 • S = X’Y’CIN+ X’YCIN’+XY’CIN’+XYCIN = ⊕ ⊕ S = X Y CIN X Y COUT CIN • COUT=XY+X CIN+Y CIN S Ch 1- 18 Flaxer Eli - Process Control

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