General Purpose list of instructions Processors Instructions are - - PowerPoint PPT Presentation

General Purpose Processors

Calcolatori Elettronici e Sistemi Operativi

Specifications

Device that executes a program

Program

list of instructions

Instructions are stored in an external memory

Stored program

Data can be read and written from/to an external memory

Universal computation

approximate

finite storage

Execution steps

Load an instruction from memory (fetch) Understand the required operation Compute Store results Detect the next instruction position

Not only linear instruction flow

jumps

Execution steps

Instruction fetch Instruction fetch Instruction decoding Instruction decoding Operand address calculation Operand address calculation Operand fetch Operand fetch Data

• peration

Data

• peration

Result store Result store Result address calculation Result address calculation Instruction address calculation Instruction address calculation

Execution steps

Instruction Fetch

Load instruction (portion) from memory

Instructions can have several formats and lenghts

Prefetch can hide memory latency and multiple lengths issue

Decode

Detect if other I-fetches are needed Decode instruction fields (operands, operation)

Execution steps

Operand address calculation

Find operands position

Register file Memory Address can depend on register or memory content

More memory reads can be required

Operand fetch

Load operands from register file Load operands from memory

Execution steps

Data operation

Perform computation through function unit

Result address computation

Find where result(s) must be stored

Registers Memory

Result store

Save data

Instruction address calculation

Find position of the next instruction

Instructions

Data manipulation

Operation

Data transfer, Arithmetic, Logic, Shift

Data type

Integer

Binary, Decimal (BCD)

Floating point

Parallelism

Scalar Vectorial

Instructions

Control flow

Conditional jumps Unconditional jumps Return from function call Return from exception Exception generation Other

Instruction repetition prefix Conditional execution

Instructions

Memory and IO access

Transfer data to and from registers Other instructions can have memory references

Data instruction operands Jump target

Other

Synchronization accesses

Atomic read-modify-write Conditional storing Bus locking prefix

Memory consistency model manipulation

Memory and execution barriers

Instructions

System management

Processor mode changes

Protection level

Interrupt enabling/disabling Processor power state changes Memory model management Cache management System identification

Special registers manipulation

Execution steps

Instruction fetch Instruction fetch Instruction decoding Instruction decoding Operand and result address calculation Operand and result address calculation Operand fetch Operand fetch Data

• peration

Data

• peration

Result store Result store Instruction address calculation Instruction address calculation

ASM chart

PC <= START_ADDR RESET MEM[PC] = INSTR1 1 INSTR1 execution MEM[PC] = INSTRi 1 INSTRi execution

PC <= PC + incr PC <= PC + disp

MEM[PC] = INSTRj 1 INSTRj execution CONDITION 1

PC <= PC + incr PC <= PC + disp

Unconditional jump Conditional jump

General scheme

ASM chart

PC <= START_ADDR RESET MEM[PC] = INSTR1 1 MEM[PC] = INSTRi 1

dp_ctrl_signals PC <= PC + incr

MEM[PC] = INSTRj 1 CONDITION 1

PC <= PC + incr PC <=PC + disp dp_ctrl_signals PC <= PC + disp dp_ctrl_signals

Combinational: MEM + DECODER

Structure

PC CTRL MEM MEM

CONTROL UNIT DATAPATH Control Signals Status Flags

Structure

PC CTRL MEM MEM

CONTROL UNIT DATAPATH Control Signals Status Flags

Timing: 1) dpREG dpREG 2) PC dpREG 3) PC PC

ASM chart

PC <= START_ADDR RESET IR <= MEM[PC] IR = INSTR1 1 IR = INSTRi 1

dp_ctrl_signals PC <= PC + incr

IR = INSTRj 1 CONDITION 1

PC <= PC + incr PC <=PC + disp dp_ctrl_signals PC <= PC + disp dp_ctrl_signals

Combinational: DECODER

Structure

PC CTRL MEM MEM

CONTROL UNIT DATAPATH Control Signals Status Flags

IR

Structure

PC CTRL MEM MEM

CONTROL UNIT DATAPATH Control Signals Status Flags

IR

Timing: 1) PC IR 2) dpREG dpREG 3) IR dpREG 4) IR PC

ASM chart

PC <= START_ADDR + incr IR <= MEM[START_ADDR] RESET IR <= MEM[PC] IR = INSTR1 1 IR = INSTRi 1

dp_ctrl_signals PC <= PC + incr

IR = INSTRj 1 CONDITION 1

PC <= PC + incr PC <=PC + disp dp_ctrl_signals PC <= PC + disp dp_ctrl_signals

Single cycle scheme Combinational: DECODER

ASM chart

PC <= START_ADDR RESET IR <= MEM[PC] PC <= PC + incr IR = INSTR1 1 IR = INSTRi 1

dp_ctrl_signals PC <= PC + incr

IR = INSTRj 1 CONDITION 1

PC <= PC + incr PC <=PC + disp dp_ctrl_signals PC <= PC + disp dp_ctrl_signals

Wait state (for branches)

Single cycle scheme with branch stall

ASM chart

IR = INSTR1 1 IR = INSTRi 1

dp_ctrl_signals PC <= PC + incr

IR = INSTRj 1 CONDITION 1

PC <= PC + incr PC <=PC + disp dp_ctrl_signals PC <= PC + disp dp_ctrl_signals

Wait state (for branches)

Single cycle scheme with branch stall

PC <= START_ADDR + incr IR <= MEM[START_ADDR] RESET IR <= MEM[PC]

ASM chart

PC <= START_ADDR RESET IR <= MEM[PC] PC <= PC + incr IR = INSTR1 1 IR = INSTRi 1

dp_ctrl_signals

IR = INSTRj 1 CONDITION 1

PC <= PC + incr PC <=PC + disp dp_ctrl_signals PC <= PC + disp dp_ctrl_signals

IR = INSTRi 1

dp_ctrl_signals

Multi-cycle instruction

Wait state (for branches)

Multi-cycle scheme

ASM chart

IR = INSTR1 1 IR = INSTRi 1

dp_ctrl_signals

IR = INSTRj 1 CONDITION 1

PC <= PC + incr PC <=PC + disp dp_ctrl_signals PC <= PC + disp dp_ctrl_signals

IR = INSTRi 1

dp_ctrl_signals

Multi-cycle instruction

Wait state (for branches)

Multi-cycle scheme

PC <= START_ADDR + incr IR <= MEM[START_ADDR] RESET IR <= MEM[PC]

Structure

PC

DEC MEM

MEM

CONTROL UNIT DATAPATH Status Flags

IR

CTRL

Pipeline registers

Control Signals

Pipeline

Multi-cycle control

Hard-wired control

Control unit FSM

Control signals for

Datapath, PC, IR, other special registers Memories

Status signals (flags) from

Functional units Flag registers Memories

Multi-cycle control

Microprogrammed control

Control unit microprogrammed FSM

µ-instruction

Control signals Datapath, PC, IR, other special registers Memories Next state info Conditions to check Addresses for next µ-instructions

Status signals (flags) from

Functional units Flag registers Memories

Microprogrammed Processor

PC COMB1

CONTROL UNIT DATAPATH Status Flags

IR CAR COMB2

+1

MEM

MEM

µ-instruction

Branch

Control Store Control Store

Address generator Control Signals

COMB3

Microprogrammed Processor

Next state

state + 1 branch

from opcode

Control signals

encoded

vertical µp

not encoded

horizontal µp

PC

increment branch

Microprogramming

Simplify development

Decouples HW and ISA design Control design becomes SW development

Flexibility

Adaptable to changes in µ-architecture, timing, technology Can make changes late in design cycle, or even in the field Can implement very powerful instruction sets

just more control memory

Microprogramming

Generality

Can implement multiple instruction sets on same machine Can tailor instruction set to application

Compatibility

Many micro-architectures, same instruction set

Microprogramming

Costly to implement

Requires a fast control memory

Slow

Microprogramming

Horizontal microprogram

no decoding larger words ( larger control store)

Vertical microprogram

smaller memory need decoding

Hybrid

“Diagonal”

Microprogramming

Enhancements

µ-instructions are buffered and executed out-of-order

Instructions are fetched and translated in µ-instructions

Translation and execution no more in lock-step

µ-instructions are cached in a special cache Special instructions sequences are recognized

Translated in special (optimized) µ-instructions sequences

Some instructions are translated through random logic

HW decoders vs Memory

Microprogramming

Microprogrammed architectures examples

IBM System/360 series (some: M30, M40, M50, M65) DEC PDP-11 DEC VAX-11 Zilog Z80 Motorola 68000 Intel

x86

CPU - interface – Von Neumann

CTRL DP INSTR/DATA

CPU - interface – Harvard

CTRL DP DATA INSTR

Datapath

Register file

symmetric

Rz <= Rx op Ry x, y, z, op

asymmetric

Function Units

Adder, Multiplier, Divider, Logic functions, Shifter, ...

cost, computational power, software complexity

Datapath

Reg File ALU

Acc

Reg File ALU Accumulator architecture

• p Rx

Symmetric architecture

• p Rd , Rs1, Rs2

Instruction Set Architecture

Memory and registers model

Size and meaning of registers

General purpose registers Special purpose registers Floating Point registers

How registers can be used by operations

Available instructions (Instruction Set)

formats, operations, data types, addressing modes

Operating modes

standard, protection levels, special modes

ISA: operands

Classification by operands number

3 operands:<instr> Rd, Rs1, Rs2

Rd <= Rs1 op Rs2 e.g., add R1, R3, R4

2 operands:<instr> Rd, Rs

Rd <= Rd op Rs e.g., add R1, R3

1 operand: <instr> Rs

acc <= acc op Rs e.g., add R3

0 operands: <instr>

M[TOP] <= M[TOP] op M[TOP+1] e.g., add use memory as a stack

ISA: memory access

Memory-to-memory

Operands are fetched/stored from/in memory

e.g., add M[Rd], M[Rs1], M[Rs2] ; M[Rd] <= M[Rs1] + M[Rs2]

Load / Store

Memory is only accessed by specific instructions

e.g.

ld R1, M[R4] ; R1 <= M[R4] ld R2, M[R5] ; R2 <= M[R5] add R3, R1, R2 ; R3 <= R1 + R2 st M[R6], R3 ; M[R5] <= R3

ISA: addressing modes

Implicit

No need to indicate the operand location (is implicit)

e.g., stack architectures

Immediate

Operand is a constant in the instruction

No need for operand fetch

Direct

The instruction contains a memory address

Operand is fetched from memory

• perand: MEM[addr]

Register

Operand is in a register, the instruction indicates the register number Operand fetch is performed in register file

ISA: addressing modes

Indirect

The instruction contains a memory address that is a pointer

Operand is fetched from memory (2 memory accesses)

• perand: MEM[MEM[addr]]

Register indirect

The instruction contains register index, the register contains a pointer

Operand is fetched from memory (access to register file and to memory)

• perand: MEM[Rs]

ISA: addressing modes

Indexed

The instruction contains an address and a displacement

Address and/or displacement can be in a register

• perand: MEM[addr + REG[x]]
• perand: MEM[addr + REG[x]*n]
• perand: MEM[REG[a] + REG[b]*n]

Others

post/pre increment/decrement

The register containing the address is incremented/decremented before/after the access Easy access to vector elements or structure fields For vectors/strings scan

Endianness

How is stored, in memory, the 32-bit number: 0x01020304 ?

0x01020304 0x01020304 Register 0x01 Memory

addr

0x02 addr+1 0x03 addr+2 0x04 addr+3

Big-endian: big end first

(680x0, SPARC, System/360, Java Virtual Machine, Internet protocols) 0x01020304 0x01020304 Register 0x04 Memory

addr

0x03 addr+1 0x02 addr+2 0x01 addr+3

Little-endian: little end first

(6502, x86, VAX, Alpha, ARM)

Bi-endian: switchable endianness

(ARM (from v3), MIPS, SPARC (from v9), Alpha (optional), PA-RISC, Power PC, SuperH)

Instruction Set

Name

Mnemonic code

Format Opcode RTL description of operation Affected flags

Instruction Set

Orthogonal

All (GP) registers can be used as operands and destinations for all of the operations Simpler SW

Less stringent constraints on resources usage

Not orthogonal

Simpler HW

Reduced wiring among registers and functional units

Reduced instruction size

Instruction format

Opcode: operating code Data fields Fixed or Variable length

• pcode
• perand
• pcode
• pcode
• perand
• perand
• pcode
• perand
• perand
• perand

inc inc EAX add EAX, EBX add R1, R4, R5

Memory model

Memory protection

Memory areas vs Operating mode

Address translation

CPU address (virtual address) Memory address (physical address)

Memory consistency

Strong consistency, Weak consistency, ...

Cache management

Flushing, cacheable/non-cacheable memory areas

Exception handling

Exception

External signals

Reset Interrupts Not maskable interrupts

Software events

Memory access

protection violation Not existing translation

Operation

Division by zero, overflow, ... Trap instructions