[PPT] - Power Reduction in Digital Circuits Ph.D. Defense Jan L an k PowerPoint Presentation

SLIDE 1

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Power Reduction in Digital Circuits

Ph.D. Defense Jan L´ an´ ık 16th June 2016

1 / 58

SLIDE 2

Introduction Power Aware Synthesis Activity Triggers Conclusions References

CIFRE Ph.D. Thesis Verimag (University of Grenoble) Industrial partner: Atrenta/Synopsys Supervisors: Oded Maler (Verimag), Fahim Rahim (Synopsys) 2012-2016

2 / 58

SLIDE 3

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Introduction

3 / 58

SLIDE 4

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Motivation

Power consumption of integrated chips is an issue Our work: yet another attempt to reduce power consumption

4 / 58

SLIDE 5

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Hardware synthesis

Hardware analog of a compilation in software High level description Silicon realization Crucial step in hardware production Optimizations for speed, space and power Many intermediate steps Many degrees of freedom

5 / 58

SLIDE 6

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Some Steps in the Hardware Synthesis

6 / 58

SLIDE 7

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Switching power dissipation at a gate

P = 1 2V 2

ddCiEif

Vdd . . . supply voltage Ci . . . capacitance connected to the output of gate i Ei . . . switching activity (number of switches per cycle)

f gate i

f . . . clock frequency

7 / 58

SLIDE 8

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Our methods

Two methods for switching activity reduction :

1 Power Aware Synthesis Optimization of combinatorial logic

synthesis

2 Activity Triggers Optimization of sequential logic blocks by

clock gating (industrial project) The two methods are independent. Common points: RTL/Netlist level, modeling input to achieve statistical switching reduction

8 / 58

SLIDE 9

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Power Aware Synthesis

9 / 58

SLIDE 10

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Our place in the synthesis flow

1) multilevel logic specification

a b c X = a · b Y = ¯ b + c y Z = X + Y z

3) Technology dependent representation

a b c y z

2ANDXU37 2ORZA15 INVBC5 2NANDXU6

2) AIG

a b c y z

10 / 58

SLIDE 11

Introduction Power Aware Synthesis Activity Triggers Conclusions References

AIG (AND-Inverter graph)

a b c y z

Acyclic directed graph Nodes: AND and NOT gates Efficient representation Not canonical Many optimizations Our method: yet another optimization on the AIG level

11 / 58

SLIDE 12

Introduction Power Aware Synthesis Activity Triggers Conclusions References

AND cones in AIG

Referred by an inverter Referred twice We want to optimize AIGs by re-arranging AND cones

12 / 58

SLIDE 13

Introduction Power Aware Synthesis Activity Triggers Conclusions References

2 ways to realize 8AND by 2ANDs

x1 x2 x3 x4 x5 x6 x7 x8 0 → 1 0 → 1 0 → 1 0 → 1 1 → 0 1 → 0 1 → 0 1 → 0 0 → 1 0 → 1 1 → 0 1 → 0 0 → 1 1 → 0 0 → 0 x1 x5 x2 x6 x3 x7 x4 x8 0 → 1 1 → 0 0 → 1 1 → 0 0 → 1 1 → 0 0 → 1 1 → 0 0 → 0 0 → 0 0 → 0 0 → 0 0 → 0 0 → 0 0 → 0

we assume synchronized design, 0 time delay 1 switch = change of value at a gate output gate values determined by input values

13 / 58

SLIDE 14

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Input stream and switching

A circuit sees more than one transition during its lifetime Input stream : sequence of values as they are applied to the circuit inputs Input stream + Internal structure = Actual switching What is a ‘typical’ input stream? Input model + Internal structure = Expected switching

14 / 58

SLIDE 15

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Input model

Ideally: Markov chain Realistically: Long input stream provided by designers

15 / 58

SLIDE 16

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Optimization and evaluation flow

16 / 58

SLIDE 17

Introduction Power Aware Synthesis Activity Triggers Conclusions References

AND Cone optimization

An AND cone is semantically equivalent to an n-input AND gate

Goal: find 2AND realization for the given cone with a minimal switching w.r.t. the typical (training) stream

Constrained to minimal-depth 2AND (timing)

17 / 58

SLIDE 18

Introduction Power Aware Synthesis Activity Triggers Conclusions References

AND Cone optimization methods

Solution:

1 Enumerative

Problem space growing fast Efficient up to approximately 8 inputs (symmetry reduction) Sufficient for most of the cones in real designs

2 Layer based approximation

Optimal on ‘layers’ Locally optimal Efficient for larger cones

18 / 58

SLIDE 19

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Balanced and unbalanced trees

19 / 58

SLIDE 20

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Number of trees to check

in all trees canonical balanced canonical & balanced 1 1 1 1 1 2 2 1 2 1 3 12 3 12 3 4 120 15 24 3 5 1680 105 480 30 6 3.0240e+04 945 4320 135 7 6.6528e+05 1.0395e+04 2.0160e+04 315 8 1.7297e+07 1.3514e+05 4.0320e+04 315 9 5.1892e+08 2.0270e+06 2.9030e+06 1.1340e+04 10 1.7643e+10 3.4459e+07 1.0161e+08 1.9845e+05 11 6.7044e+11 6.5473e+08 2.2353e+09 2.1830e+06 12 2.8159e+13 1.3749e+10 3.3530e+10 1.6372e+07 13 1.2953e+15 3.1623e+11 3.4871e+11 8.5135e+07

20 / 58

SLIDE 21

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Layer based cone synthesis

layer-optimal

Each pairing of input signals into an AND gate produces certain switching number. Minimizing the switchings in the first level corresponds to minimal perfect matching in a weighted graph O(n3), Edmonds65, Lawrer76.

21 / 58

SLIDE 22

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Examples of suboptimality

x1 x2 x3 x4 x5 x6 x7 x8 0→0→0 0→1→0 0→1→0 0→1→1 0→1→1 0→1→1 1→1→0 1→1→1 0→0→0 0→1→0 0→1→1 1→1→0 0→0→0 0→1→0 0→0→0 x1 x2 x3 x7 x4 x5 x6 x8 0→0→0 0→1→0 0→1→0 1→1→0 0→1→1 0→1→1 0→1→1 1→1→1 0→0→0 0→1→0 0→1→1 0→1→1 0→0→0 0→1→1 0→0→0

A level-greedy pairing An optimal pairing with 6 switches with 5 switches

22 / 58

SLIDE 23

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Examples of suboptimality: missing topologies

x1 x2 x3 x4 x5 x6 0→1 1→0 0→1 1→0 0→1 0→1 0→0 0→0 0→0 0→1 0→0 x1 x2 x3 x5 x4 x6 0→1 1→0 1→0 0→1 0→0 0→1 0→1 0→0 0→0 0→0 0→0

(a) (b)

23 / 58

SLIDE 24

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Evaluation scenarios

We evaluate on 2 classes of examples:

1 Synthetic products of Markov chains

Different forms of interaction/correlation between variables Another parameter characterizes the amount of randomness/determinism

2 Verilog models of 2 small designs

A simple decoder for a hand held calculator A Serial Peripheral Interface from Opencores

24 / 58

SLIDE 25

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Synthetic examples

25 / 58

SLIDE 26

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Small realistic circuits

Net effect of our method on AIG level maximum minimum level-greedy Mini Instruction Decoder 250338 128118 158726 Core SPI (opencores) 20577 19681 19681 Interference due to other optimization methods maximum minimum level-greedy Mini Instruction Decoder 73976 72288 72288 Core SPI (opencores) 19555 19233 19233

26 / 58

SLIDE 27

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Shortcomings

Preprocessing diminishes the savings Unclear if reduction preserved on mapped netlist

27 / 58

SLIDE 28

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Activity Triggers

28 / 58

SLIDE 29

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Clock gating

Disabling registers when not needed by ‘gating the clock’ to save power

clk

CG

en data D Q

ut

gated clk

clk en gated clk Problem: How to compute the enabling condition?

29 / 58

SLIDE 30

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Clock gating conditions - granularity

Coarse grained Design decision On the high level - whole functional blocks Handcrafted enable conditions Efficient, easy to implement, high in the clock tree Fine grained Small register groups deep in the designs Complex, not intuitive Need tools to find them Can be expensive

30 / 58

SLIDE 31

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Clock gating conditions - granularity

Intermediate Missing link Medium sized blocks Understandable, but not necessarily obvious Human designer should be able to find them if he did a time consuming detailed analysis Tools in demand

31 / 58

SLIDE 32

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Activity Triggers

Events related to a change of activity status of a design block.

MODULE ACTIVE MODULE IDLE β α

32 / 58

SLIDE 33

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Example

TRANSMITER RECEIVER uart UART clk rst rx transmit tx_byte[7:0] received recv_byte[7:0] is_receiving recv_error is_transmitting tx

CNT

ut reg

inp reg CNT

CONTROL

FSM

CONTROL

FSM

33 / 58

SLIDE 34

Introduction Power Aware Synthesis Activity Triggers Conclusions References

UART - serial line transmission

line idle start bit 1 1 1 0 0 1 two stop bits line idle data transmission

34 / 58

SLIDE 35

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Tool components

1 Detection of potential triggers 2 Formal verification (my contribution) 35 / 58

SLIDE 36

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Statistical detection

Correlation analysis performed on vcd or fsdb traces generated from simulation For detection we consider only events that are bit/bus transitions. E.g. a signal x going from 0 to 1 or a 4-bit bus Y going from 4′b0001 to 4′b0010

1 design decomposition 2 idle periods detection 3 potential events filtering (based on size and sequential

distance)

4 ranking potential events (coverage and ran measures) 36 / 58

SLIDE 37

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Potential start and stop signals location

Stop events · · · in a short window before the beginning of stable periods Start events · · · in a short window before the end of stable periods

37 / 58

SLIDE 38

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Ranking of events

Coverage · · · the ratio of idle periods that are correlated with the event Noise · · · the ratio of events that are ‘out of place’

38 / 58

SLIDE 39

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Formalization

An activity trigger is a triple (α, β, d) α . . . start condition β . . . stop condition d . . . shutdown delay

39 / 58

SLIDE 40

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Monitor automaton

MODULE ACTIVE ¬β ∨ α MODULE IDLE α ∧ stable · · · ¬α β ∨ ¬α ¬α ¬α d−1 delay nodes α α α ¬α ∧ stable PROPERTY VIOLATION ¬stable

40 / 58

SLIDE 41

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Formalization (PLTL)

Stability of a signal: stable(x) = (x ∧ ⊖(x)) ∨ (¬x ∧ ⊖(¬x)) Stability of a block (set of signals): stable(M) =

x∈M

stable(x)

41 / 58

SLIDE 42

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Formalization (PLTL)

Stop Condition: ⊖dβ ∧

d

i=0

⊖i¬α Start condition: α

42 / 58

SLIDE 43

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Formal Verification

We need to prove: ¬αS

⊖dβ ∧

d

i=0

⊖i¬α

⇒ stable(M)

43 / 58

SLIDE 44

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Stability modeling

D Q EN

regn data en

D Q

stable(regn)

i stable(regi)

stable(regn−1)

44 / 58

SLIDE 45

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Monitor automaton

MODULE ACTIVE ¬β ∨ α MODULE IDLE α ∧ stable · · · ¬α β ∨ ¬α ¬α ¬α d−1 delay nodes α α α ¬α ∧ stable PROPERTY VIOLATION ¬stable

45 / 58

SLIDE 46

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Formal verification flow

1 Original RTL ⇒ circuit representation 2 Stability modeling and monitor automaton added to the circuit 3 Verification using reachability engines from ABC

(BMC + PDR)

46 / 58

SLIDE 47

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Constraint support

Implicit assumptions often not present in the design Can be added in form of assertions Typical cases: configuration registers or input following specific pattern This is crutial to avoid spurious counter examples We support System Verilog Assertions (SVA)

47 / 58

SLIDE 48

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Automatic flow

48 / 58

SLIDE 49

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Semi-automatic flow

49 / 58

SLIDE 50

Introduction Power Aware Synthesis Activity Triggers Conclusions References

SENDS – A video processing architecture

50 / 58

SLIDE 51

Introduction Power Aware Synthesis Activity Triggers Conclusions References

SENDS results

51 / 58

SLIDE 52

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Automatic mode results

design power power covered 1 4.169 mW 75.84% 2 7.163 mW 54.93% 3 0.479 mW 49.62% 4 7.145 mW 49.47% 5 5.314 µW 31.04% 6 0.606 mW 16.30% 7 8.891 mW 15.58% 8 92.491 mW 6.77% 9 55.851 mW 4.54% 10 92.444 mW 2.87% 11 1.430 µW 1.61% 12 4.079 mW 0.70% 13 149.955 mW 0.61%

52 / 58

SLIDE 53

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Conclusions

53 / 58

SLIDE 54

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Activity Triggers: Summary

New class intermediate-block-size clock gating conditions Heuristic detection based on trace analysis Formal proof of validity Semi-automatic and automatic methodology Integrated within a commercial tool

54 / 58

SLIDE 55

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Activity Triggers: Limitations

Constraints Room for improvement in scalability Room for improvement in detection

55 / 58

SLIDE 56

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Power Aware Synthesis: Summary

Power Aware Synthesis Optimizing switching in combinational logic Average case optimization Implemented as prototype within ABC Experimented on synthetic as well as realistic models Works well on AIG level

56 / 58

SLIDE 57

Introduction Power Aware Synthesis Activity Triggers Conclusions References

Power Aware Synthesis: Limitations

Interference from other optimization techniques Unclear if switching reduction can be preserved in the next synthesis steps

57 / 58

SLIDE 58

Introduction Power Aware Synthesis Activity Triggers Conclusions References

References I

Jan Lanik and Oded Maler. “On Switching Aware Synthesis for Combinational Circuits”. In: Hardware and Software: Verification and Testing. Ed. by Nir Piterman. Vol. 9434. Lecture Notes in Computer Science. Springer International Publishing, 2015, pp. 276–291. Jan Lanik et al. “Reducing power with activity trigger analysis”. In: Formal Methods and Models for Codesign (MEMOCODE), 2015 ACM/IEEE International Conference

n. IEEE. 2015, pp. 169–178.

Thank you!

58 / 58