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Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s

Introduction to Structured VLSI Design ‐ FSM’s

Joachim Rodrigues

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s

Overview

• State Machines
• Moore
• Mealy
• Exercise

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s

Mealy vs. Moore

• Moore

– Out = F(Current state) – Next state = F(Inputs, current state)

S1 Y=0 A1 A2 Y S4 Y=1 S2 Y=0 10 01 S3 Y=1 11 A1 A2 = 00

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s

Mealy vs. Moore

• Mealy

– Out = F(Inputs, Current state) – Next state = F(Inputs, Current state)

S1 A1 A2 Y S4 S2 10/0 01/1 00/0 S3 11/1 10/0 11/1 01/1 A1 A2 / Y

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s

Mealy vs. Moore

• In some situations a Mealy machine can be specified

and implemented using less states because it is capable of producing different outputs in a given state.

• In some situations a system using a Mealy machine

can be faster because an output may be produced immediately instead of at the next clock tick.

• A Moore machine produces glitch free outputs.
• The outputs from a Moore machine are available to

its environment for almost a clock cycle, and in some situations this may allow using a faster cock.

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s

Mealy

FSM1 FSM2 R A S0 0/0 S1 1/1 1/1 0/0

• When in s0, a Mealy machine may produce A‐>1

immediately in response to R‐>1

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s

Moore

FSM1 FSM2 R A S0 A=0 S1 A=1 1 1

• … a Moore machine is not able to produce A‐>1 until

the next clock when it enters s1

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s

• Pushing: * { A; B; B; A } => Open
• Draw a state graph for the Lock‐FSM

A small exercise /problem

Lock FSM

Clk A B

Open

1

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s

State Graph for lock‐FSM

s0 L=0 sAB L=0 s1 L=0 sA L=0 s3 L=0 sABB L=0 s2 L=0 sABBA L=1

A A B B B B A A A A Assuming that A and B are never pressed at the same time …

sABBB L=0

B B A etc…

Hmmm: Is this a Mealy FSM or a Moore FSM?

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s

FSM Exercise (”Homework”)

Marge wants to install an alarm that triggers as soon as somebody enters the kitchen. The alarm should have several alert levels.

• level0: Neither Homer nor Bart is in the kitchen
• level1: Bart but not Homer is in the kitchen
• level2: Homer but not Bart is in the kitchen
• level3: Homer and Bart are in the kitchen

To detect who enters or leaves the kitchen 2 sensors g1 and g0 are installed in the door frame as depicted. The sensors emit a ‘1’ as soon as their reflection is

• interrupted. If Bart enters the kitchen only g0 will emit a ‘1’. Homer is always

leaning forward when he is entering the kitchen, and, thus, g1 will always be interrupted before g0. Once they have decided to go into the kitchen they will go through the door. However, if they are in the kitchen they always can leave, e.g., level3 changes to level2. The size of Homers hips and belly prevent them from entering the kitchen simultaneously. The clock frequency is 1MHz.

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s