Finite State Machine (FSM) Model of behaviour composed of a finite - PowerPoint PPT Presentation

Finite State Machine (FSM) • Model of behaviour composed of a finite number of states, input events, transitions between those states (rules or conditions), and actions. Inputs State conditionA S1 S0 / / !conditionB !conditionA value1 value0 conditionB Outputs

Sequential systems Feedback / Sequential logic current next Comb. Outputs D Q Inputs logic clk Synchronous logic • Sequential systems are synchronous, i.e. makes use of a clock • Outputs are dependent on earlier and the current state of inputs

Finite State Machines in HW • Requires registers to store the current state, a block of combinational logic to determine the next state (transition), and a block of combinational logic to determine the output of the FSM (MEALY ONLY) OUTPUTS INPUTS STATE NEXT OUTPUT MEMORY STATE LOGIC LOGIC CLK CURRENT STATE

Moore Machine OUTPUTS INPUTS STATE NEXT OUTPUT MEMORY STATE LOGIC LOGIC CLK CURRENT STATE • Outputs are a function of the current state only • Outputs are synchronous to the clock • Propagation delay through output logic may nevertheless lead to hazards (glitches) • A Moore machine has a one clock period delay from input to output.

Mealy Machine OUTPUTS INPUTS STATE NEXT OUTPUT MEMORY STATE LOGIC LOGIC CLK CURRENT STATE Outputs are a function of the current state and the inputs • Outputs change immediately when the input change* • Combinational path through FSM – Outputs of mealy machine is one clock cycle ahead of a Moore Machine (faster) • But has more complicated decoding of outputs • *In an FPGA it is generally recommended to synchronize all signals to the system clock. I.e., it is expected that the inputs are synchronous to the same clock as the state memory. Essentially the outputs of a Mealy machine are therefore also synchronous to the clock. The main difference is that the output changes one clock cycle ahead of the current state, and therefore the Moore machine.

Description of state machines • State diagrams Graphic representation of state machine • ASM diagram • State table

State graph/diagram Moore Inputs State conditionA s S0/ s S1/ !conditionB !conditionA value0 value1 conditionB Outputs

State graph/diagram Mealy Inputs Outputs State conditionA / value1 !conditionB / s S0 !conditionA / s S1 value1 value0 conditionB / value0

ASM false condition true Conditional output box Decision box State box The state box represents the state in the FSM with a list of outputs values that are • assigned when entering the state. The decision box checks input condition to determine exit path of current ASM block • A conditional output box lists output assignments that should take place when exiting • the state (Mealy outputs). Can only be placed after exit path of decision box.

ASM State entry State entry false condition false condition true ASM block true State exit ASM block State exit Unique exit path for a given combination of inputs • Exit path of ASM block must always lead to state box. •

ASM diagram Moore False conditionA True False conditionB True

ASM diagram Mealy conditionA False True conditionB False True

State table Moore Current state next state next state Current output condiationA !conditionA conditionB !conditionB S0 S1 S0 - - value0 S1 - - S0 S1 value1

State table Mealy Current conditionA !conditionA conditionB !conditionB state next state output next state output next state output next state output S0 S1 value1 S0 value0 - - - - S1 - - - - S0 value0 S1 value1