I I I -V MOSFETs for Future CMOS J. A. del Alamo, D. A. Antoniadis, - - PowerPoint PPT Presentation

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I I I -V MOSFETs for Future CMOS J. A. del Alamo, D. A. Antoniadis, - - PowerPoint PPT Presentation

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I I I -V MOSFETs for Future CMOS J. A. del Alamo, D. A. Antoniadis, J. Lin, W. Lu, A. Vardi and X. Zhao Microsystems Technology Laboratories Massachusetts Institute of Technology IEEE Compound Semiconductor IC Symposium New Orleans, LA;

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I I I -V MOSFETs for Future CMOS

  • J. A. del Alamo,
  • D. A. Antoniadis, J. Lin, W. Lu, A. Vardi and X. Zhao

Microsystems Technology Laboratories Massachusetts Institute of Technology

IEEE Compound Semiconductor IC Symposium New Orleans, LA; October 11-14, 2015

Acknowledgements:

  • Sponsors: DTRA, Lam Research, Northrop Grumman, NSF, Samsung
  • Labs at MIT: MTL, EBL
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Contents

1. Motivation: Moore’s Law and MOSFET scaling 2. Planar InGaAs MOSFETs 3. InGaAs FinFETs 4. Nanowire InGaAs MOSFETs 5. Conclusions

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  • 1. Moore’s Law at 50: the end in sight?

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Moore’s Law

Moore’s Law = exponential increase in transistor density

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Intel microprocessors

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Moore’s Law

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?

How far can Si support Moore’s Law?

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1 2 3 4 5 6 1980 1985 1990 1995 2000 2005 2010 2015 Supply voltage (V) Year of introduction

Transistor scaling  Voltage scaling  Performance suffers

Transistor current density (planar MOSFETs):

Transistor performance saturated in recent years

Intel microprocessors Intel microprocessors

Supply voltage:

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SLIDE 7

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Moore’s Law: it’s all about MOSFET scaling

Enhanced gate control  improved scalability

  • 1. New device structures:

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Moore’s Law: it’s all about MOSFET scaling

  • 2. New materials:

Si  Strained Si  SiGe  InGaAs Si  Strained Si  SiGe  Ge  InGaSb

Future CMOS might involve two different channel materials with two different relaxed lattice constants!

del Alamo, Nature 2011 (updated)

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I I I -V electronics in your pocket!

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  • 2. Self-aligned Planar I nGaAs MOSFETs

Lin, IEDM 2012, 2013, 2014 W Mo Lee, EDL 2014; Huang, IEDM 2014 selective MOCVD Sun, IEDM 2013, 2014 Chang, IEDM 2013 reacted NiInAs dry-etched recess implanted Si + selective epi

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Self-aligned Planar I nGaAs MOSFETs @ MI T

Lin, IEDM 2012, 2013, 2014

Recess-gate process:

  • CMOS-compatible
  • Refractory ohmic contacts (W/Mo)
  • Extensive use of RIE

W Mo

0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.2 0.4 0.6 0.8 1.0 Lg=20 nm

Ron=224 Ω.µm 0.4 V

Id (mA/µm) Vds (V)

Vgs-Vt= 0.5 V

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  • Channel: In0.7Ga0.3As/InAs/In0.7Ga0.3As
  • Gate oxide: HfO2 (2.5 nm, EOT~ 0.5 nm)

Highest performance I nGaAs MOSFET

  • Record gm,max = 3.1 mS/µm at Vds= 0.5 V
  • Ron = 190 Ω.µm
  • 0.4
  • 0.2

0.0 0.2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

gm,max= 3.1 mS/µm Lg = 80 nm Vds= 0.5 V

gm (mS/µm) Vgs (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Id (mA/µm) Vds (V)

Vgs = -0.3 to 0.4 V in 0.1 V step Lg = 80 nm Ron=190 Ω.µm

Lg =80 nm, tc=9 nm Lin, IEDM 2014

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Excess OFF-state current

OFF-state current enhanced with Vds  Band-to-Band Tunneling (BTBT) or Gate-Induced Drain Leakage (GIDL)

Lin, IEDM 2013

  • 0.6 -0.4 -0.2 0.0

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Lg=500 nm Vds=0.3~0.7 V step=50 mV

Id(A/µm) Vgs (V)

Transistor fails to turn off:

Vds ↑

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  • 0.4 -0.2 0.0 0.2

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W/ BTBT+BJT W/O BTBT Vds=0.3~0.7 V step=50 mV

Id (A/µm) Vgs (V)

Excess OFF-state current

Lg↓  OFF-state current ↑  additional bipolar gain effect due to floating body

Lin, EDL 2014

  • 0.6 -0.4 -0.2 0.0

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Lg=500 nm Vds=0.3~0.7 V step=50 mV

Id(A/µm) Vgs (V)

  • 0.6 -0.4 -0.2 0.0

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500 nm 280 nm 120 nm T=200 K Vds=0.7 V

Id (A/µm) Vgs-Vt (V)

Lg=80 nm

Vds ↑

Simulations

w/ BTBT+BJT w/o BTBT+BJT

Lg=500 nm

Lin, TED 2015

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Planar I nGaAs MOSFET scaling

  • tc ↓  S ↓ but also gm,max ↓
  • Even at tc=3 nm, Lg,min~40 nm

 planar MOSFET at limit of scaling

Lin, IEDM 2014 Lin, TED 2015

0.01 0.1 1 10 1 2 3

gm,max (mS/µm)

Lg(µm)

4 nm tc=9 nm 11 nm 12 nm 7 nm 3 nm 8 nm

Vds=0.5 V

0.01 0.1 1 10 100 200 300 400

Smin (mV/dec)

Lg(µm)

Vds=0.5 V

tc ↓ 3 nm Vds=0.5 V tc=12 nm

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500 1000 1500 2000 2500 3000 3500 1980 1990 2000 2010

gm (μS/μm) Year

InGaAs HEMT InGaAs MOSFET

Benchmarking: gm in MOSFETs vs. HEMTs

del Alamo, ESSDERC 2013 (updated)

MIT MOSFETs

– Very rapid recent progress in MOSFET gm – Best MOSFETs now match best HEMTs – No sign of stalling  more progress ahead! gm of InGaAs MOSFETs vs. HEMTs (any VDD, any Lg):

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  • 3. I nGaAs FinFETs and Trigate MOSFETs

Kim, IEDM 2013

60 nm Dry-etched fins Epi-grown fin inside trench

Si

Wf=30 nm

Waldron, VLSI Tech 2014

Aspect-Ratio Trapping

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I nGaAs FinFETs @ MI T

Vardi, DRC 2014, EDL 2015, IEDM 2015

0.0 0.1 0.2 0.3 0.4 0.5 5 10 15 20 Wf=12 nm VGS=0 V

ID [µA/µm] VDS [V]

VGS=0.5 V

Lg=5 μm

Fin etch by RIE

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  • 4. Nanowire I nGaAs MOSFETs

Waldron, EDL 2014 Tomioka, Nature 2012 Persson, EDL 2012

Nanowire MOSFET: ultimate scalable transistor

Tanaka, APEX 2010

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Lateral vs. Vertical Nanowire MOSFETs

Yakimets, TED 2015 Bao, ESSDERC 2014

Vertical NW: uncouples footprint scaling from Lg and Lc scaling  power, performance and area gains wrt. Lateral NW

5 nm node

30% area reduction in 6T-SRAM 19% area reduction in 32 bit multiplier

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I nGaAs Vertical Nanowires on Si by direct growth

Björk, JCG 2012 Selective-Area Epitaxy Au seed Vapor-Solid-Liquid (VLS) Technique InAs NWs on Si by SAE Riel, MRS Bull 2014

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I nGaAs VNW-MOSFETs fabricated via top-down approach @ MI T

Zhao, IEDM 2013

Top-down approach: flexible and manufacturable

15 nm 240 nm Key enabling technologies:

  • BCl3/SiCl4/Ar RIE
  • digital etch

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Process flow

Tomioka, Nature 2012 Persson, DRC 2012

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D= 30 nm NW-MOSFET

Single nanowire MOSFET:

  • D=30 nm
  • Lch= 80 nm
  • 4.5 nm Al2O3 (EOT = 2.2 nm)

At VDS=0.5 V:

  • gm,pk=280 μS/μm
  • Ron=759 Ω.μm

0.0 0.1 0.2 0.3 0.4 0.5 Vds (V)

Vgs=-0.6 V to 0.8 V in 0.1 V step Ron=759 Ω.µm (at Vgs=1 V)

50 100 150 200

Id (µA/µm

)

  • 0.6 -0.4 -0.2 0.0

0.2 0.4 0.6 50 100 150 200

Vgs (V)

50 100 150 200 250 300

gm, pk(Vds=0.5 V) =280 µS/µm

Vds=0.5 V Id (µA/µm) gm (µS/µm)

Zhao, IEDM 2013

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Conclusions

1. Great recent progress on planar, fin and nanowire III-V MOSFETs 2. Vertical Nanowire III-V MOSFET: superior scalability and power/performance characteristics 3. Vertical Nanowire n- and p-type III-V MOSFET: plausible path for co-integration on Si 4. Many demonstrations of InGaAs VNW MOSFETs by bottom-up and top-down approaches 5. Many issues to work out…

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A lot of work ahead but… exciting future for I I I -V electronics

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