I I I -V MOSFETs for Future CMOS J. A. del Alamo, D. A. Antoniadis, J. Lin, W. Lu, A. Vardi and X. Zhao Microsystems Technology Laboratories Massachusetts Institute of Technology IEEE Compound Semiconductor IC Symposium New Orleans, LA; October 11-14, 2015 Acknowledgements: • Sponsors: DTRA, Lam Research, Northrop Grumman, NSF, Samsung • Labs at MIT: MTL, EBL
Contents 1. Motivation: Moore’s Law and MOSFET scaling 2. Planar InGaAs MOSFETs 3. InGaAs FinFETs 4. Nanowire InGaAs MOSFETs 5. Conclusions 2
1. Moore’s Law at 50: the end in sight? 3
Moore’s Law Moore’s Law = exponential increase in transistor density Intel microprocessors 4
Moore’s Law How far can Si support Moore’s Law? ? 5
Transistor scaling Voltage scaling Performance suffers Transistor current density Supply voltage: (planar MOSFETs): 6 5 Supply voltage (V) 4 3 2 1 Intel microprocessors Intel microprocessors 0 1980 1985 1990 1995 2000 2005 2010 2015 Year of introduction Transistor performance saturated in recent years 6
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Moore’s Law: it’s all about MOSFET scaling 1. New device structures: Enhanced gate control improved scalability 8
Moore’s Law: it’s all about MOSFET scaling 2. New materials: Si Strained Si SiGe InGaAs Si Strained Si SiGe Ge InGaSb Future CMOS might involve two different channel materials with two different relaxed lattice constants ! del Alamo, Nature 2011 (updated) 9
I I I -V electronics in your pocket! 10
2. Self-aligned Planar I nGaAs MOSFETs dry-etched recess selective MOCVD W Mo Lin, IEDM 2012, 2013, 2014 Lee, EDL 2014; Huang, IEDM 2014 implanted Si + selective epi reacted NiInAs Sun, IEDM 2013, 2014 Chang, IEDM 2013 11
Self-aligned Planar I nGaAs MOSFETs @ MI T W Mo 1.0 L g =20 nm V gs -V t = 0.5 V Lin, IEDM 2012, 2013, 2014 R on =224 Ω.µ m 0.8 I d (mA/ µ m) 0.4 V 0.6 Recess-gate process: 0.4 • CMOS-compatible 0.2 • Refractory ohmic contacts (W/Mo) 0.0 • Extensive use of RIE 0.0 0.1 0.2 0.3 0.4 0.5 V ds (V) 12
Highest performance I nGaAs MOSFET • Channel: In 0.7 Ga 0.3 As/InAs/In 0.7 Ga 0.3 As • Gate oxide: HfO 2 (2.5 nm, EOT~ 0.5 nm) L g =80 nm, t c =9 nm 1.4 3.5 V gs = -0.3 to 0.4 V in 0.1 V step g m,max = 3.1 mS/ µ m 1.2 L g = 80 nm 3.0 R on =190 Ω.µ m 1.0 I d (mA/ µ m) 2.5 g m (mS/ µ m) 0.8 2.0 0.6 1.5 L g = 80 nm 0.4 1.0 0.2 0.5 V ds = 0.5 V 0.0 0.0 0.0 0.1 0.2 0.3 0.4 0.5 -0.4 -0.2 0.0 0.2 V ds (V) V gs (V) • Record g m,max = 3.1 mS/ µ m at V ds = 0.5 V • R on = 190 Ω.µ m Lin, IEDM 2014 13
Excess OFF-state current Transistor fails to turn off: L g =500 nm -5 10 V ds ↑ I d (A/ µ m) -7 10 -9 10 V ds =0.3~0.7 V step=50 mV -11 10 -0.6 -0.4 -0.2 0.0 V gs (V) OFF-state current enhanced with V ds Band-to-Band Tunneling (BTBT) or Gate-Induced Drain Leakage (GIDL) Lin, IEDM 2013 14
Excess OFF-state current -4 L g =500 nm 10 -5 T=200 K 10 V ds =0.7 V V ds ↑ -5 10 I d (A/ µ m) I d (A/ µ m) -7 10 -6 10 L g =80 nm -7 -9 10 10 120 nm 280 nm V ds =0.3~0.7 V -8 10 step=50 mV 500 nm -11 10 -0.6 -0.4 -0.2 0.0 -0.6 -0.4 -0.2 0.0 V gs (V) V gs -V t (V) Simulations W/ BTBT+BJT w/ BTBT+BJT -5 10 W/O BTBT Lin, EDL 2014 w/o BTBT+BJT L g =500 nm I d (A/ µ m) Lin, TED 2015 -7 10 L g ↓ OFF- state current ↑ -9 10 additional bipolar gain effect due to V ds =0.3~0.7 V step=50 mV -11 floating body 10 -0.4 -0.2 0.0 0.2 V gs (V) 15
Planar I nGaAs MOSFET scaling Lin, IEDM 2014 Lin, TED 2015 400 3 t c =9 nm S min (mV/dec) t c =12 nm g m,max (mS/ µ m) 300 t c ↓ 8 nm 2 V ds =0.5 V 11 nm V ds =0.5 V 200 7 nm 12 nm 1 3 nm 100 4 nm V ds =0.5 V 3 nm 0 0 0.01 0.1 1 10 0.01 0.1 1 10 L g ( µ m) L g ( µ m) • t c ↓ S ↓ but also g m,max ↓ • Even at t c =3 nm, L g,min ~40 nm planar MOSFET at limit of scaling 16
Benchmarking: g m in MOSFETs vs. HEMTs g m of InGaAs MOSFETs vs. HEMTs (any V DD , any L g ): 3500 3000 2500 MIT MOSFETs g m ( μ S/ μ m) InGaAs HEMT 2000 1500 1000 InGaAs MOSFET 500 del Alamo, ESSDERC 2013 0 (updated) 1980 1990 2000 2010 Year – Very rapid recent progress in MOSFET g m – Best MOSFETs now match best HEMTs – No sign of stalling more progress ahead! 17
3. I nGaAs FinFETs and Trigate MOSFETs Dry-etched fins 60 nm Kim, IEDM 2013 Si Epi-grown fin inside trench Aspect-Ratio W f =30 nm Trapping Waldron, VLSI Tech 2014 18
I nGaAs FinFETs @ MI T 20 W f =12 nm V GS =0.5 V L g =5 μ m 15 I D [ µ A /µ m] 10 Fin etch by RIE 5 V GS =0 V 0 0.0 0.1 0.2 0.3 0.4 0.5 V DS [V] Vardi, DRC 2014, EDL 2015, IEDM 2015 19
4. Nanowire I nGaAs MOSFETs Waldron, EDL 2014 Persson, Tomioka, Nature 2012 Tanaka, APEX 2010 EDL 2012 Nanowire MOSFET: ultimate scalable transistor 20
Lateral vs. Vertical Nanowire MOSFETs 5 nm node Yakimets, TED 2015 Bao, ESSDERC 2014 30% area reduction in 6T-SRAM 19% area reduction in 32 bit multiplier Vertical NW: uncouples footprint scaling from L g and L c scaling power, performance and area gains wrt. Lateral NW 21
I nGaAs Vertical Nanowires on Si by direct growth Au seed InAs NWs on Si by SAE Selective-Area Epitaxy Vapor-Solid-Liquid (VLS) Technique Riel, MRS Bull 2014 Björk, JCG 2012 22
I nGaAs VNW-MOSFETs fabricated via top-down approach @ MI T 15 nm 240 nm Key enabling technologies: • BCl 3 /SiCl 4 /Ar RIE Zhao, IEDM 2013 • digital etch Top-down approach: flexible and manufacturable 23
Tomioka, Nature 2012 Process flow Persson, DRC 2012 24
D= 30 nm NW-MOSFET V gs =-0.6 V to 0.8 V in 0.1 V step 200 300 R on =759 Ω.µ m (at V gs =1 V) g m, pk (V ds =0.5 V) 200 =280 µ S/ µ m 250 150 I d ( µ A/ µ m ) g m ( µ S/ µ m) 150 ) I d ( µ A/ µ m 200 100 150 100 100 V ds =0.5 V 50 50 50 0 0 0 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.0 0.1 0.2 0.3 0.4 0.5 V ds (V) V gs (V) Single nanowire MOSFET: • D=30 nm • L ch = 80 nm • 4.5 nm Al 2 O 3 (EOT = 2.2 nm) At V DS =0.5 V: g m,pk =280 μ S/ μ m • R on =759 Ω . μ m • Zhao, IEDM 2013 25
Conclusions 1. Great recent progress on planar, fin and nanowire III-V MOSFETs 2. Vertical Nanowire III-V MOSFET: superior scalability and power/performance characteristics 3. Vertical Nanowire n- and p-type III-V MOSFET: plausible path for co-integration on Si 4. Many demonstrations of InGaAs VNW MOSFETs by bottom-up and top-down approaches 5. Many issues to work out… 26
A lot of work ahead but… exciting future for I I I -V electronics 27
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