FEMBs Design of FEMBs with LArASIC, ColdADC, FPGA/COLDATA Jack - PowerPoint PPT Presentation

FEMBs Design of FEMBs with LArASIC, ColdADC, FPGA/COLDATA Jack Fried on behalf of the CE group February 6 , 2020

Outline • FEMB History • FEMB Versions – LArASIC + P1 ADC + FPGA – LArASIC + ColdADC + FPGA – LArASIC + ColdADC + COLDATA • FEMB Data Cable – FPGA – COLDATA • FEMB Power Cable – FPGA – COLDATA • FEMB lessons learned – FEMB diagnostics – Connector issue – FEMB unique address 2/6/2020 2

Frontend Board Experience • Cold electronics development – MicroBooNE – 35-ton – ProtoDUNE-SP – SBND – DUNE 2/6/2020 3

Cold Electronics CE flange Warm electronics Flange assembly with cable Warm Interface Electronics Crate strain relief and flange PCB - Warm Interface Board for cable/WIB connection - Power and Timing Card - Power and Timing Backplane ProtoDUNE CE Cold cables Cables used for low voltage and data/clock transport to FEMB’s Front End Motherboard (FEMB) 128 channels of digitized wire readout enclosed in CE Box 2/6/2020 4

What all FEMBs have in common • 128 input channels • Discrete input protection • Data cable – TX link to warm – Slow control – Synchronous timing control • Cold regulators • Low voltage cable • CE BOX 2/6/2020 5

Cold Electronics FEMB FPGA based – FPGA based • LArASIC + P1 ADC + FPGA • LArASIC + ColdADC + FPGA – COLDATA based • LArASIC + ColdADC + COLDATA COLDATA based Signal & power needs for each type 2/6/2020 6

ProtoDUNE FEMB P2 LArASIC P1 ADC FPGA (COTS) 128:4 multiplexing ~6mW/ch ~14mW/ch ~16mW/ch 1 x 8 x 7 2/6/2020

ProtoDUNE FEMB • Currently in use at ProtoDUNE – 120 boards used for over one year with no board failures • Consists of two boards – FPGA Mezzanine -- 14 Layer PCB FPGA Mezzanine (FM) – Analog Motherboard --10 Layer PCB • FPGA Mezzanine – One Altera Cyclone IV FPGA – 3.6V, 2.8V,1.5V & 5V bias over 4 pairs on power cable – Analog monitor over power cable • 128 channel DUNE Analog Motherboard (AM) – 8 x P2 LArASIC ASIC’s • Four on top four on bottom – 8 x P1 ADC ASIC’s • Four on top four on bottom Analog Motherboard (AM) – 2.2V and 5V bias supply over 4 pairs • 12 pair Samtec data cable • 9 pair Samtec power cable 2/6/2020 8

LArASIC + P1 ADC + FPGA 2 2 4 4 pairs pairs pairs pairs LVDS LVDS LVDS FEMB • Data Cable IO (12 Pairs) CLK TX SCL FPGA JTAG SYNC/CMD LINK SDA & AMON – 1.28Gb TX data link (4 pairs) – I2C link (2 pairs) FPGA • SDA bidir bussed LVDS CS CS • SCL standard LVDS SCK SCK SDI SDI – 100MHz Clock SDO SDO ADC DATA – SYNC/CMD FPGA Mezzanine • 2MHz DC balanced PWM signal Analog ADC ASIC ADC ASIC ADC ASIC ADC ASIC Motherboard (synchronous commands) ADC ASIC ADC ASIC ADC ASIC ADC ASIC – CS CS CS CS JTAG (4 pairs) SCK SCK SCK SCK SDI SDI SDI SDI • Single ended signals used to update FPGA SDO SDO SDO SDO firmware • FEMB ASIC configuration LArASIC LArASIC LArASIC LArASIC LArASIC LArASIC LArASIC LArASIC • Eight independent SPI links controlled by CS CS CS CS the FPGA SCK SCK SCK SCK SDI SDI SDI SDI • Each SPI link has one ADC and LArASIC SDO SDO SDO SDO FROM APA 2/6/2020 9

LArASIC + P1 ADC + FPGA Regulators Analog Motherboard 2X FPGA Mezzanine TPS74201 TPS74201 3.6V 2.2V P1 ADC VDDD 5V bias 5V bias 3.3V 1.8V TPS74201 TPS74201 P1 ADC VDDA 2.2V 2.8V 1.8V 2.5V TPS74201 TPS74201 LArASIC VDDA 2.8V 2.2V 1.8V 1.8V TPS74201 TPS74201 LArASIC VDDP 1.5V 2.2V 1.2V 1.8V 2/6/2020 10

LArASIC + ColdADC + FPGA FPGA (COTS) LArASIC ColdADC 64:2 multiplexing ~24mW/ch 64:2 ~6mW/ch ~26mW/ch multiplexing 8 x ColdADC runs at 64MHz instead of 200MHz 2 x calling for a wider bus, requiring two FPGA for meet IO needs 2/6/2020 11

“ LArASIC + ColdADC + FPGA” FEMB • First FEMB with new ColdADC • Consists of two boards FPGA Mezzanine (FM) – FPGA mezzanine -- 16 Layer PCB – Analog Motherboard --10 Layer PCB • FPGA Mezzanine – Two Altera Cyclone IV FPGA – 3.6V, 2.8V,1.5V & 5V bias over 4 pairs – Analog monitor over power cable • 128 channel DUNE Analog Motherboard (AM) – 8x ColdADC V1 chips ~22mW/ch – 8x LArASIC P2/P3 chips ~6mW/ch – POWER AM • 4.2V and 5V bias supply over 4 pairs (ProtoDUNE WIB) • 2.8V , 2.2V and 5V bias supply over 4 pairs (new DUNE WIB) • Fully compatible with current ProtoDUNE WIB hardware and Firmware* – Identical data format/channel mapping as ProtoDUNE FEMB Analog Motherboard (AM) – *4 resistors on WIB to be replaced for raising AM supply voltage – *Configuration scripts will require an update to control ColdADC 2/6/2020 12

LArASIC + ColdADC + FPGA 2 1 2 2 1 4 pairs pairs pairs pairs LVDS LVDS LVDS • Data Cable IO (12 Pairs) – ADDR 1 ADDR 0 1.28Gb TX data link (4 pairs) FEMB TX TX LINK LINK • 2 for each FPGA FPGA JTAG CLOCK CLOCK & AMON FPGA – FPGA I2C link (2 pairs) SYNC/ SYNC/ CMD CMD CMOS • CMOS SDA bidir bussed LVDS LArASIC (SPI) LArASIC (SPI) SDA SDA • SCL standard LVDS SCL SCL SCL SCL CMOS CMOS SDA W2C – SDA W2C 100MHz Clock SDA C2W(4) SDA C2W(4) FPGA – SYNC/CMD Mezzanine Analog Motherboard • 2MHz DC balanced PWM signal (synchronous commands) – Cold ADC Cold ADC JTAG (4 pairs) Cold ADC Cold ADC Cold ADC Cold ADC Cold ADC Cold ADC • Single ended signals used to update FPGA SCL SCL SCL SCL SDA W2C SDA W2C firmware SDA W2C SDA W2C SDA C2W SDA C2W SDA C2W SDA C2W • TDO can be used as an analog monitor • FPGA Shared signal form WIB LArASIC LArASIC LArASIC LArASIC LArASIC LArASIC – LArASIC LArASIC 100MHz clock CS CS CS CS – SCK SCK SCK SCK SYNC/CMD SDI SDI SDI SDI SDO SDO SDO SDO – I2C link • FEMB ASIC configuration – Eight independent SPI links for LArASIC’s – Eight ColdADC I2C links four per FPGA FROM APA 2/6/2020 13

“ LArASIC + ColdADC + FPGA” FEMB Regulators 2X Analog Motherboard FPGA Mezzanine TPS74201 3.6V TPS74201 2.8V 5V bias ColdADC VDDA 5V bias 3.3V 2.25V TPS74201 TPS74201 ColdADC VDDD 2.8V 2.8V 2.5V 2.25V TPS74201 TPS74201 2.8V 2.8V ColdADC VDDIO 2.25V 2.25V TPS74201 TPS74201 ColdADC VDDD 2.8V 2.2V 1.8V 1.2V TPS74201 TPS74201 LArASIC VDDA 1.5V 2.2V 1.2V 1.8V TPS74201 LArASIC VDDP 2.2V 1.8V 2/6/2020 14

“ LArASIC + ColdADC + dual FPGA” FEMB Tested at both RT and LN ProtoDUNE WIB ProtoDUNE 7m power cable ProtoDUNE 7m data cable 2/6/2020 15

LArASIC + ColdADC + COLDATA COLDATA LArASIC ColdADC 64:2 multiplexing ~6mW/ch 64:2 multiplexing ~6mW/ch ~26mW/ch 8 x 2 x 2/6/2020 16

LArASIC + ColdADC + COLDATA • Consists of two boards – COLDATA mezzanine -- 12 Layer PCB* – Analog Motherboard --10 Layer PCB COLDATA Mezzanine (FM) • COLDATA Mezzanine – Two COLDATA ASIC’s – 2.8V, 2.0 & 5V bias over 3 pairs • 128 channel DUNE Analog Motherboard (AM) – 8x ColdADC V1 chips – 8x LArASIC P2/P3 chips – Identical to FPGA version – POWER AM • 4.2V and 5V bias supply over 4 pairs (ProtoDUNE WIB) • 2.8V , 2.2V and 5V bias supply over 4 pairs (new DUNE WIB) • ProtoDUNE WIB Firmware is not compatible with this FEMB – New firmware required – Resistors on ProtoDUNE WIB need to be moved and replaced – Configuration scripts will require an update Analog Motherboard (AM) 2/6/2020 17

LArASIC + ColdADC + COLDATA 1 1 1 2 3 2 pairs pair pairs pairs pair pair LVDS LVDS LVDS LVDS LVDS LVDS • Data Cable IO (10 Pairs) FEMB TX TX SCL CLOCK CLOCK LINK LINK SDA W2C • SDA C2W 1.28Gb TX data link (4 pairs) COLDATA COLDATA FCMD FCMD slave master • 2 for each COLDATA CMOS CMOS LArASIC (SPI) LArASIC (SPI) • I2C link (3 pairs) SCL CMOS SCL SCL SCL CMOS CMOS SDA W2C SDA W2C SDA W2C SDA W2C SDA C2W SDA C2W • SDA C2W(4) SDA C2W(4) SDA_W2C standard LVDS • Coldata Mezzanine SDA_C2W standard LVDS Analog Motherboard • SCL standard LVDS • Cold ADC Cold ADC Cold ADC Cold ADC 2 X 62.5MHz Clock Cold ADC Cold ADC Cold ADC Cold ADC • SCL SCL SCL SCL FAST COMMAND SDA W2C SDA W2C SDA W2C SDA W2C SDA C2W SDA C2W SDA C2W SDA C2W • Synchronous commands LArASIC LArASIC LArASIC LArASIC • COLDATA Shared signal form WIB LArASIC LArASIC LArASIC LArASIC CS CS CS CS • Fast Command SCK SCK SCK SCK SDI SDI SDI SDI SDO SDO SDO SDO • COLDATA I2C relay • COLDATA has a master slave topology the master COLDATA ASIC interfaces to the WIB using standard LVDS and relays the I2C link to the slave FROM APA COLDATA and the eight ColdADC ASIC’s • Eight independent SPI links for LArASIC’s four links per COLDATA 2/6/2020 18