Testing ColdADC ASICs at UF Ivan Furic, UF Shanshan Gao, BNL - - PowerPoint PPT Presentation

Testing ColdADC ASICs at UF

Ivan Furic, UF Shanshan Gao, BNL

Things we learned even before starting

• Never transport test board with an ASIC in the socket
• Regardless of the excellent padding of the two boards and package,
• ne ASIC fell out of socket, other got jammed in the socket
• Pins are so fine that they will bend if the chip just falls on its side / corner

ASIC was jammed in socket Unsuccessful attempt at straightening pins manually

Why this matters

• ColdADC are significantly more delicate than ProtoDUNE ASICs
• Have significantly more (delicate) pins
• Damage Rate: one chip (out of 46) due to manual placement in socket

ColdADC damaged during manual placement ProtoDUNE ADC ASIC

Hardware Setup

• Taken from detailed instructions provided by Shanshan (BNL)

BNL ColdADC test board wired up

ADC Input from SRS-360 ColdADC Test socket 10 MHz Reference Optical Link (Readout) Power Supplies

SRS WF Generator (+10MHz Reference) RIGOL Power Supplies DAQ PC Basket-Dunking Tower Test Board in basket (board is submerged) Wide-Bore Dewar Flask N2 Gas Line

UF UF Cr Cryo Te Test Stand:

ColdADC Testing Software

• Overall really well written, push-button suite of Python code that

performs tests, collates all the plots (per channel x per reference type x per sampling rate)

• Not an extension of the BNL ProtoDUNE QA/QC software suite
• Similarities exist, likely started from a branch earlier than most of the

HEP-user-friendly features were added for ProtoDUNE testing, e.g.

• Linux port + ROOT output [Windows + binary data record]
• Locking: only one instance of HW-controlling SW can run at a time
• automatic command line versions of python function calls
• Test-driving GUI with intermediate result display
• Automatic standard output (console log) capture

ColdADC Testing software stages

Tests cover (in rough order):

• Manually entered Board + Chip ID (does not overwrite previous tests)
• Calibrates BJT and CMOS references
• Linearity of references
• All communication modes (should be run first)
• Manually runs “automatic” calibration
• Sinewave-based ADC non-linearity mapping (DNL, INL)
• Sine-wave signal (~14 kHz, ~28 kHz) to noise (ENOB)
• Out-of-range warnings / errors for some of the quantities

All gathered test data are preserved in “raw” binary format,

• therwise directory structure would be ready for archiving (+time stamp)

Full cycle for a chip test

• Dry off cables with N2: 2-3 minutes
• Set up board (+fast pre-check): 3-5 minutes
• Immersion (2 minutes)
• Test (15-20 minutes)
• Return from cryo (5 minutes)
• Baking in dehydrator (15 minutes at 55 deg C)

[done in parallel with testing of next chip]

• Estimate avg flow of 30 mins / chip
• QC testing procedures are not final
• some tests may be shortened, others extended or done differently

Types of serious failures that we have seen

• ADC appears ok at room temp, pulls > 3A current on ASIC input in LN2
• ADC appears ok at room temp, pulls no current on ASIC in LN2
• ADC appears ok at room temp, pulls ok current in LN2, can’t calibrate

references - stuck in pseudo-infinite loop

• No input to ADC (likely fixed by checking 50 Ohm termination)
• Rates not credible yet, need to eliminate possibility of socket / board

issues, will re-test most “failures” once first full pass is done

Failed dunks suck

• ”Failed” LN2 dunk:
• results are inconclusive or don’t make sense
• Indication of comms loss during test
• Not even a full checkout in warm

guarantees a successful LN2 result

• Minimum (fast) tests at room

temperatupre:

• Power up in basket, check currents
• Check all connections when in basket
• Check 50 Ohm termination of ADC input SMA

All DNL / INL curves differ from BNL findings

ALL SINAD / ENOB plots also differ (related?)

Comparison of Bulk Properties - DNL

@UF @BNL

Comparison of bulk properties: INL

@UF @BNL

Comparison of Bulk Properties: ENOB

@UF @BNL

Comparison of Bulk Properties: Noise @ 900 mV

@UF @BNL

Comparison of Bulk Properties - Summary

• Performance properties can only be grossly compared between test

stands

• Test stands differ in at least two components:
• Keysight PS vs Rigol PS provides voltages to ADC
• Additional 100MHz timing module synchronizes board and signal generator
• Significant bump in INL curve @ UF casts doubt on sine-wave method

as being robust for determining an actual calibration curve

Other Findings

• Substantial wear+tear / “dirt” on SMA cable connectors (unexpected)

Current status

• Received 89 chips from FNAL, two chips from BNL
• Both BNL chips were damaged in transport
• Ran tests on 47 chips, breakdown
• Damaged chips: 1
• Certain Fail: 2
• Certain pass: 34
• Need re-test: 10 (at least 3: expect due to faulty board setup)
• As of 02/19, handed off testing chips to grad student Mayank Tripathi
• spent part of Summer 2019 testing SBND ADCs @ BNL using MSU CTS
• needed minimal additional training – how to dunk into an open-flask dewar
• This week, plan to further expand to up to three undergrads to maximize live time
• Shanshan sent us two more test boards (one of the boards seems to be failing)

Looking Forward

• Presented first results on cold-testing ColdADCs at a University setting
• BNL has provided a push-button QA suite that can be used for QC
• In ~2wk (IKF part time), tested roughly half of the ASICs
• Some SW restructuring and features are needed to use current SW suite for

straightforward and fast QC method

• Need to discuss common strategy for future code development
• Don’t want to implement user-useful changes to this code, then have to do that all
• ver again for the next chip / board iteration
• Despite considerable efforts, not able to get bulk properties to fully line up
• Can tell a good chip from a bad one, in principle QC works
• INL/DNL derived with sine wave method are not robust