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T42 Transputer Design in FPGA Transputer Design in FPGA T42 Year- -Two Design Status Report Two Design Status Report Year a and Martin ZABEL b , Uwe MIELKE a Uwe MIELKE and Martin ZABEL b , in collaboration w/ Michael BRUESTLE c c

  1. T42 � � Transputer Design in FPGA Transputer Design in FPGA T42 Year- -Two Design Status Report Two Design Status Report Year a and Martin ZABEL b , Uwe MIELKE a Uwe MIELKE and Martin ZABEL b , in collaboration w/ Michael BRUESTLE c c in collaboration w/ Michael BRUESTLE a E E lectronics Engineer, Dresden, Germany, lectronics Engineer, Dresden, Germany, uwe.mielke@t uwe.mielke@t- -online.de online.de a b I I nstitut of Computer Engineering, Technische Universit nstitut of Computer Engineering, Technische Universitä ät Dresden, Germany, t Dresden, Germany, martin.zabel@tu martin.zabel@tu- -dresden.de dresden.de b c Electronics Engineer, Vienna, Austria, c Electronics Engineer, Vienna, Austria, michael_bruestle@yahoo.com michael_bruestle@yahoo.com Communicating Process Architectures 2016

  2. T42 in FPGA @ CPA 2016 T42 in FPGA @ CPA 2016 Abstract : Abstract : This fringe session will present the design progress of This fringe session will present the design progress of our IMS- -T425 compatible Transputer design in FPGA. T425 compatible Transputer design in FPGA. our IMS The 32bit CPU + Memory interface (2x8kB) are in The 32bit CPU + Memory interface (2x8kB) are in stable working condition. 117 instructions (from stable working condition. 117 instructions (from 123+7) are almost implemented in 460 lines of uCode, 123+7) are almost implemented in 460 lines of uCode, e.g. TASM loops incl. interruptible MOVE(s) can be e.g. TASM loops incl. interruptible MOVE(s) can be simulated some 100 clock cycles. Timer(s) are running. simulated some 100 clock cycles. Timer(s) are running. The System control unit allows error mode, MOV- -bit bit The System control unit allows error mode, MOV and events. Some still open questions around scheduler and events. Some still open questions around scheduler micro- -code and link interaction will be discussed. code and link interaction will be discussed. micro CPA 2016

  3. Agenda Achievements (2016 vs 2015) (1) T42 Schematic Overview (2) T42 VHDL Top View (2016 vs 2015) (3) uCode � News (4) Status Bits for Mov2D (5) CPU : Cache : DDR-RAM-Ctrl = 1 : 2 : 4 (6) Outlook (2016 vs 2015) (7) Discussion: Links � (and uCode interaction) (8) CPA 2016

  4. T42 in FPGA @ CPA 2014 2014 T42 in FPGA @ CPA Our Motivation: Our Motivation: � Overcome absence of CSP (Transpu ters and Occam) in public Overcome absence of CSP (Transpu ters and Occam) in public � � Provide a free, IMS Provide a free, IMS - -T425 binary compatible, open source VHDL T425 binary compatible, open source VHDL � � Many T42 cores fit into s mall FPGA Many T42 cores fit into s mall FPGA e.g. 2 in XC6S � e.g. 2 in XC6S- -LX9 LX9 � � 16+ in XC2S 16+ in XC2S- -LX100 LX100 � VHDL is easy to download, easy to improve VHDL is easy to download, easy to improve � � let let � � s enhance it ! s enhance it ! � � Computer Engineering Students need toys to play with ! Computer Engineering Students need toys to play with ! � � TU Dresden has experience with own Java MultiCore in FPGA TU Dresden has experience with own Java MultiCore in FPGA � My (U.M.) personal motivation: My (U.M.) personal motivation: I bunched into concurrency in 1983 � � my diploma thesis: my diploma thesis: � � a RTOS for Z80 a RTOS for Z80 � � I bunched into concurrency in 1983 � � I � � m addicted to transputers since 1984 = concurrency elegance in h m addicted to transputers since 1984 = concurrency elegance in hardware ! ardware ! I � � old foil from CPA 2014

  5. T42 Achievements 2015 2015 T42 Achievements � T42 Project started May T42 Project started May � � 2013 2013 � � VHDL Design started Jan VHDL Design started Jan � � 2014 2014 � � Data path and control path (1st concept) working Data path and control path (1st concept) working � � Apr Apr � � 2014 2014 � � Microcode Assembler (12 AWK scripts) completed Microcode Assembler (12 AWK scripts) completed � � Jan Jan � � 2015 2015 � � ~50 simple OpCodes implemented, datapath extended Apr ~50 simple OpCodes implemented, datapath extended Apr � � 2015 2015 � � Pipeline running (from 8 byte prefetch buffer) Pipeline running (from 8 byte prefetch buffer) � � May May � � 2015 2015 � � onChip memory added (ldnl, stnl, onChip memory added (ldnl, stnl, � � ) and verified ) and verified � � Jun Jun � � 2015 2015 � � Prefetch state machine + Iptr Prefetch state machine + Iptr - -Incrementor verified Incrementor verified � � Jul Jul � � 2015 2015 � � System control unit, statu s bits, more flags added System control unit, statu s bits, more flags added * * � � Aug Aug � � 2015 2015 � i.e. core infrastructure is almost almost complete, but complete, but � � still * t.b. verified still * t.b. verified i.e. core infrastructure is old foil from CPA 2015

  6. T42 Achievements 2016 T42 Achievements 2016 � System control unit, statu s bits to Sreg connected System control unit, statu s bits to Sreg connected � � Aug Aug � � 2015 2015 � � Timer VHDL (not fully te sted yet, uCode missing !) Timer VHDL (not fully te sted yet, uCode missing !) � � Sep Sep � � 2015 2015 � � Pipelined Oreg within Idecode (hardware Pfix,Nfix) Pipelined Oreg within Idecode (hardware Pfix,Nfix) � � Nov Nov � � 2015 2015 � � Move+Move2D: ByteAlign + uCode + Mov Move+Move2D: ByteAlign + uCode + Mov - -bit Ok bit Ok � � Feb Feb � � 2016 2016 � � MemIF w/ dual port arbit er completed (8kB + 8kB) MemIF w/ dual port arbit er completed (8kB + 8kB) � � Apr Apr � � 2016 2016 � � uCode for long Arithmetics, Error Mode tested Ok uCode for long Arithmetics, Error Mode tested Ok � � May May � � 2016 2016 � � uCode for In, Out, ALT uCode for In, Out, ALT � � s (no timer ! still ongoing) s (no timer ! still ongoing) � � Jun Jun � � 2016 2016 � � Scheduler uCode (some 1st routines, still ongoing) Scheduler uCode (some 1st routines, still ongoing) � � Jul Jul � � 2016 2016 � � 1st trial VHDL of (the m ost simple) Output Link 1st trial VHDL of (the m ost simple) Output Link � � Aug Aug � � 2016 2016 � Note: >460 lines uCode written (from 512, i.e. uCodeROM is almost full)! Note: >460 lines uCode written (from 512, i.e. uCodeROM is almos t full)! Intension was to understand influence of uCode influence of uCode on DataPath+Sytem structure. on DataPath+Sytem structure. Intension was to understand CPA 2016

  7. Example: Mov2DnonZero NextAction=1 i.e. MOVE is interuptible MOV-bit MOV2D-bits

  8. T42 Schematic 2016 T42 Schematic 2016 Timers 8kB 512x DPRAM 96bit T42-CPU uCode (On-Chip) ROM Fetch Addr and and Instr. Data Bus Bus Link 0-3 2nd & DMA � s (N/A) 8kB DPRAM (preliminary System instead of Services Caches) CPA 2016

  9. Remark: Blocks in red Remark: Blocks in red still N/A. still N/A. T42 VHDL Top View 2015 2015 T42 VHDL Top View T42cpu_all_top (structural) SysPath : T42_cpu_constpkg � SysCtrl, Sbits, Timer, SysService Ctrl2Data (structural) � Pipeline MemPath : � MemIF CtrlPath : DataPath : Target Board No.2 199$ � MemMain Digilent ATLYS � uCodeROM � ABCDEreg (2kx32) MemDDR2 � Idecode � ALU X+Y=Z (64Mx16 on board) � Oreg � Wptr XC6LX45 � Iptr (+Inc) � Pointers � DCache � PreFetch � ConstBox � ICache Target Board No.1 89$ � DataOutBus � eMemIF Avnet Micro Board MemLPDDR LinkPath: (32Mx16 on board XC6LX9 old foil from CPA 2015

  10. Remark: Blocks in red Remark: Blocks in red still N/A. still N/A. T42 VHDL Top View 2016 T42 VHDL Top View 2016 T42cpu_all_top (structural) Target Board No.3 99$ Target Board No.3 99$ Digilent Arty Digilent Arty SysPath : T42_cpu_constpkg MemDDR3 MemDDR3 � SysCtrl, Sbits, Timer, SysService (128Mx16 on board) (128Mx16 on board) XC7A35T XC7A35T Ctrl2Data (structural) � Pipeline MemPath : � MemIF CtrlPath : DataPath : Target Board No.2 199$ Target Board No.2 199$ Target Board No.2 199$ � MemMain � � Digilent ATLYS Digilent ATLYS Digilent ATLYS uCodeROM ABCDEFreg (dpram2kx32) � MemDDR2 MemDDR2 MemDDR2 � Idecode ALU X+Y=Z � (64Mx16 on board) (64Mx16 on board) (64Mx16 on board) � Oreg (pipe) Wptr preliminary � XC6LX45 XC6LX45 XC6LX45 � � Iptr (+Inc) Pointers � instead of cache � � � PreFetch ConstBox DummyCache Target Board No.1 89$ Target Board No.1 89$ Target Board No.1 89$ � ByteAlign (dpram2kx32) Avnet Micro Board Avnet Micro Board Avnet Micro Board MemLPDDR MemLPDDR MemLPDDR available+tested: LinkPath : (32Mx16 on board (32Mx16 on board (32Mx16 on board � CacheCtrl (TUD) � XC6LX9 XC6LX9 XC6LX9 Sync, ChIn, ChOut, ChEvent, Ifos � DDRCtrl (TUD) CPA 2016

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