LArASIC - FE ASIC for DUNE LAr TPC Dr. Venkata Narasimha Manyam - - PowerPoint PPT Presentation

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LArASIC - FE ASIC for DUNE LAr TPC Dr. Venkata Narasimha Manyam - - PowerPoint PPT Presentation

Mar 05, 2023 242 likes •711 views

LArASIC - FE ASIC for DUNE LAr TPC Dr. Venkata Narasimha Manyam Instrumentation Division, Brookhaven National Laboratory February 6th, 2020, CERN Outline LArASIC Introduction Changes Between Recent LArASIC Versions LArASIC P3

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SLIDE 1

LArASIC - FE ASIC for DUNE LAr TPC

  • Dr. Venkata Narasimha Manyam

Instrumentation Division, Brookhaven National Laboratory February 6th, 2020, CERN

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SLIDE 2
  • LArASIC Introduction
  • Changes Between Recent LArASIC Versions
  • LArASIC P3 Simulations and Identified Issues
  • LArASIC P4 Development
  • LArASIC P4 Simulations
  • Summary and Future Work

Outline

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SLIDE 3

LArASIC – Simplified block diagram & functionality

  • 16 channels
  • Two-stage charge amplifier, high-order filter (5th)
  • Adjustable Reset Quiescent Current (RQI/leakage)

settings (100 pA, 500 pA, 1nA, 5 nA)

  • Adjustable gain: 4.7, 7.8, 14, 25 mV/fC

(Max. charge 55, 100, 180, 300 fC)

  • Adjustable filter time constant

(peaking time 0.5, 1, 2, 3 µs)

  • Selectable collection/non-collection mode

(baseline 200, 900 mV)

  • Selectable DC/AC coupling (100µs HPF time-const.)
  • Rail-to-rail analog signal processing with single-ended

buffer

  • Bandgap referenced (BGR) biasing circuits
  • Temperature sensor (~ 3mV/°C)
  • Integrated 6-bit pulse generator
  • 144 configuration registers, SPI interface
  • 5.5 mW/channel (input MOSFET 3.9 mW)
  • ~ 16,000 MOSFETs
  • Designed for room (300K) and cryogenic (77K) operation
  • Technology CMOS 0.18 µm, 1.8 V, 6M, MIM, SBRES

3

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SLIDE 4

Previous FE ASIC layout

6.0 mm 5.7 mm

*P2 AISC

Successful deployment with excellent performance at MicroBooNEand ProtoDUNE

4

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SLIDE 5

LArASIC Channel – Simplified block diagram

Charge Amplifier Shaper AC/DC

Adaptive Continuous Reset (ACR)

Buffer

RQI/leakage

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SLIDE 6

Changes between recent versions of the FE ASIC

P1 (V6)

  • 6-bit pulse generator added
  • SLKH, i.e., high (10x) Reset-loop

Quiescent Current (RQI) added to compensate for saturation effects (aka “Chirping”)

  • BGR fix didn’t work → 7% chips

don’t start in cold

  • RQI subtraction added in CA2 to

correct for BL DC for 5nA RQI → CA2 Adaptive Continuous Reset (ACR) non-functional → needs 1GOhm at input

  • Transistor sizing similar to V5
  • Imperfect PZ cancellation → return

to baseline issues

P2 (V7)

  • PA-SH changed to correct return to

baseline issue

  • Removed RQI subtraction in CA2
  • Changed W and L in the ACR of CA1

and CA2

  • {W,L} in ACR CA2, P2 = {8*W,

8*L} ACR CA2, P1

  • Inter-channel BL variation

(geometric dependence) for 200 mV BL option observed due to packaging stress

  • Ledge observed only in cold during

shower event (after P3 tape-out)

  • BGR issue of 7% chips in cold still

present

P3 (V8)

  • Geometric dependence for 200 mV

baseline mitigated by replacing current biasing with voltage in shaper 1st and 2nd stages → changes CA2 bias vol.

  • Ledge behavior still present in cold
  • BGR issue of 7% chips in cold still

present

6

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SLIDE 7
  • Identified problems
  • Bandgap Voltage Reference (BGR) fails in 7% of the chips
  • Ledge effect during shower event
  • Simulation procedure
  • Model files from foundry used
  • “cmno18_asp_v1d2.scs” in BSIM4 (V4.5)
  • Extrapolated for LN and LAr temperatures, outside of guaranteed range
  • Mismatch models only for MOSFETs
  • Perform different analysis needed such as DC, AC, stability (STB), noise , transient (with
  • r/and without noise) in nominal, process corners (SS, FF, SF and FS) and Monte Carlo with

process variation (PV) and mismatch (MM)

  • Schematic level simulations have been shown later

Outline of Identified problems and simulation methodology

Only in Cold

  • peration

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SLIDE 8

BGR Problem in P3

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SLIDE 9

Bias module based on Bandgap Voltage Reference (BGR)

  • Still 7% of the P3 chips doesn’t start only in cold → They are currently screened-off

BGR Bias module

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SLIDE 10

P3 BGR simulations

1 (33) 2(36,32) 1 (43)

4 runs out of 50 show problem at cold

50 run MonteCarlo(PV+MM) sim.s with Temp. sweep -196 to 125°C Expected ~ 1.2 V

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SLIDE 11

Start-up sim.s of P3 BGR

2 runs (21, 43) out of 50 show problem at cold by settling to ~ supply (1.775 V)

1µs supply ramping; 50 run MC (PV+MM) at LAr and RT

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SLIDE 12

Ledge Effect in P3

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SLIDE 13

Ledge effect in LArASIC P3

Image from: Study of the “Ledge” effect in protoDUNE readout, Hucheng Chen, et al.

  • Only during cold operation and mostly with shower charge (e.g. > 100 fC for 14 mV/fC setting)

for 200 mV baseline setting, LArASIC P2 and P3 outputs of some of the channels saturate and produce ledge characteristic after a delay

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SLIDE 14

Simulation of shower event at LN : 500 fC input for 50 µs

LArASIC V5 (V4*) LArASIC P3

tPeak = 1 µs Leakage = 500 pA BL = 200 mV Gain = 14 mv/fC Cdet = 150 pF

No ledge effect with

  • ld and new models

TT_m196 → rf018.scs is BSIM3 (V3.24) ~17k lines TT_new_m196 → cmno18_asp_v1d2.scs is BSIM4 (V4.5) ~38k lines

180 nm TSMC tech. model files Red: old model Yellow: new model Ledge effect only observed with new models (BSIM4) and not with old (BSIM3)

50 µs 50 µs 14

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SLIDE 15

Origin of ledge effect

  • Adaptive Continuous Reset(ACR) network in

the ca2n resized from V5(V4*)/V6(P1) moving to V7(P2)/V8(P3) to improve pole-zero cancellation (baseline restoration)

  • Width and Length of the transistors in ACR

increased by 8 times in P3 compared to V5, increased gate cap. by ~64 times, making the loop unstable, causing ledge

Both W and L increased by 8 times

Ledge effect origin fully understood

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SLIDE 16

Other Performance Metrics of P3

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SLIDE 17

Simulations of P3 channel baseline DC shift for different settings

0.226 0.233 0.245 0.258 0.000 0.100 0.200 0.300 0.400 0.500 0.600 0.700 0.5 µs 1 µs 2 µs 3 µs

Baseline DC (V) for 200 mV BL

100 pA 500 pA 1 nA 5 nA 0.927 0.934 0.947 0.959 0.700 0.800 0.900 1.000 1.100 1.200 1.300 1.400 0.5 µs 1 µs 2 µs 3 µs

Baseline DC (V) for 900 mV BL

100 pA 500 pA 1 nA 5 nA

* Setting: BL = 200/900 mV, Gain = 14 mV/fC, Cdet = 150 pF

RQI (leakage) setting of 500 pA mostly used and 5 nA is not needed Baseline shift reduces signal swings ΔV = 32 mV ΔV = 32 mV

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SLIDE 18

P3 ASIC baseline DC variation in LN – Measurement of 171 chips, 2736 channels

Setting: BL = 200/900 mV, Gain = 14 mV/fC, Tp = 2 us, DC, Buffer on, 500pA. 1.6% had unresponsive channels and 4.79% did not respond after a power cycle in LN

4 40 160 360 546 733 546 308 88 20 10 1 100 200 300 400 500 600 700 800 200 210 220 230 240 250 260 270 280 290 300 More Frequency Bin (mV)

200 mV BL

6 4 132 513 814 857 401 77 9 2 1 100 200 300 400 500 600 700 800 900 850 860 870 880 890 900 910 920 930 940 950 More Frequency Bin (mV)

900 mV BL

Mean (mV) 243.78

  • Std. dev. (mV)

15.95 Mean (mV) 898.88

  • Std. dev. (mV)

12.87

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SLIDE 19

P3 FE ASIC baseline DC variation in LN – MC simulations

100 run MC simulations (PV+MM) at schematic level Setting: BL = 200/900 mV, Gain = 14 mV/fC, Tp = 2 us, DC coupling, Buffer not used, 500pA, Cdet = 150 pF Bandgap reference voltage problem (1.78 V instead of 1.2 V) in 6% (200 mV BL) and 4% (900 mV BL) simulation runs

1 3 7 14 12 14 23 11 5 3 1 5 10 15 20 25 200 210 220 230 240 250 260 270 280 290 300 Frequency Bin (mV)

200 mV BL

Mean (mV) 245.1

  • Std. dev. (mV)

20.23 1 4 10 17 22 25 14 3 5 10 15 20 25 30 900 910 920 930 940 950 960 970 980 990 Frequency Bin (mV)

900 mV BL

Mean (mV) 945.8

  • Std. dev. (mV)

14.52

Close to measurements

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SLIDE 20

Simulations of P3 channel ENC

555.6 423.7 369.6 372.4 100 200 300 400 500 600 700 800 0.5 µs 1 µs 2 µs 3 µs

ENC (e-) for 200 mV BL

100 pA 500 pA 1 nA 5 nA 557.8 424.7 369.8 372.5 100 200 300 400 500 600 700 800 0.5 µs 1 µs 2 µs 3 µs

ENC (e-) for 900 mV BL

100 pA 500 pA 1 nA 5 nA

Setting: BL = 200/900 mV, Gain = 14 mV/fC, Cdet = 150 pF

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SLIDE 21

P3 Simulation results – Linearity

< |0.07|% for full range

  • 5.00E-04
  • 4.00E-04
  • 3.00E-04
  • 2.00E-04
  • 1.00E-04

0.00E+00 1.00E-04 2.00E-04 3.00E-04 20 40 60 80 100 120 Residuals (V) Charge (fC)

Residual Plot

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 20 40 60 80 100 120 vOut (V) Charge (fC)

Output voltage vs Input charge INL = ± 23 m% (Compatible with 12 bits)

Setting: BL = 200 mV, Gain = 14 mV/fC, Tp = 2 us, 500pA, Cdet = 150 pF

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SLIDE 22

Single-ended output buffer linearity

  • 2.00E-07
  • 1.50E-07
  • 1.00E-07
  • 5.00E-08

0.00E+00 5.00E-08 1.00E-07 1.50E-07 2.00E-07 2.50E-07 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Residuals (V) vIn (V)

Residual Plot

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 vOut (V) vIn (V)

Output voltage vs Input voltage INL = ± 14 µ% (Typical)

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SLIDE 23

LArASIC P4 Development

  • Towards a robust design

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SLIDE 24
  • Required
  • Address bandgap voltage reference failures happening in ~7% of the chips at cold
  • Ledge effect mitigation during shower events up to 500 fC input charge
  • Implement single ended to differential buffer matching with ADC spec.s
  • Additional
  • Decreasing baseline shift for different settings

Required Improvements for New FE ASIC (P4)

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SLIDE 25

BGR Problem Mitigation in P4

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SLIDE 26

Mitigation of Bandgap Reference problem with schematic modifications for P4

In all the previous versions of BGR, bias of BGR was derived from BGR → Problem We decoupled it

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SLIDE 27

50 run MC (PV+MM) sim.s with Temp. sweep -196 to 125°C of proposed BGR

All 50 runs pass

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Start-up sim.s of proposed BGR with 1µs supply ramping; 10 run MC (PV+MM) at LAr and RT

10 runs with different noise seed in transient noise for each MC run All 200 runs (100 LAr and 100 RT) pass

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SLIDE 29

Ledge Effect Mitigation in P4

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SLIDE 30

Proposed mitigation of Ledge Effect

  • After multiple simulations the optimal

resizing factor was chosen to be 3x instead of 8x

  • Capacitance increases by factor 9, not 64
  • Mitigates ledge effect
  • Pole-zero cancellation similar to P3

Both W and L increased by 3 times instead of 8

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SLIDE 31

Simulations of shower event at LN for P4 : 500 fC input for 50 µs

tPeak = 1 µs Leakage = 500 pA BL = 200 mV Gain = 14 mv/fC, Cdet = 150 pF

No Ledge/saturation observed even for 5X maximum input charge (100 fC)

50 µs 31

P3 channel output for same input and settings

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SLIDE 32

Monte-Carlo simulation of shower event at LN for P4 : 500 fC input for 50 µs

10 run with process and mismatch at schematic level

tPeak = 1 µs Leakage = 500 pA BL = 200 mV Gain = 14 mv/fC, Cdet = 150 pF 50 µs 32

No Ledge/saturation observed even for 5X maximum input charge (100 fC) P3 channel output for same input and settings

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SLIDE 33

Monte-Carlo simulation of shower event at LN for P4 : 1 pC input for 50 µs

100 run with process and mismatch at schematic level

tPeak = 1 µs Leakage = 500 pA BL = 200 mV Gain = 14 mv/fC, Cdet = 150 pF 50 µs 33

No Ledge/saturation observed even for 10X maximum input charge (100 fC) P3 channel output for same input and settings (2 dead channels + 98 Ledge)

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SLIDE 34

Baseline DC Shift Improvement in P4

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SLIDE 35

RQI subtraction by 16x

Proposed mitigation of baseline shift for different settings

  • RQI subtraction improves baseline shift
  • A factor of 16x RQI is optimal
  • Previously in P1, all the RQI was completely

subtracted (20x) in P1, which incapacitates adaptive continuous reset loop (leakage). Hence necessitating 1 GΩ resistor at input to make the loop work.

4x 4x

20x 20x

1x 1x 35

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SLIDE 36

Baseline shift for different settings with Proposed modifications

0.223 0.224 0.227 0.229 0.000 0.100 0.200 0.300 0.400 0.500 0.600 0.700 0.5 µs 1 µs 2 µs 3 µs

Baseline DC (V)

100 pA 500 pA 1 nA 5 nA 0.929 0.930 0.933 0.935 0.700 0.800 0.900 1.000 1.100 1.200 1.300 1.400 0.5 µs 1 µs 2 µs 3 µs

Baseline DC (V)

100 pA 500 pA 1 nA 5 nA

Setting: BL = 200/900 mV, Gain = 14 mV/fC, Cdet = 150 pF

Baseline shift improved → Maximizes signal swings ΔV = 6 mV (32 mV for P3) ΔV = 6 mV (32 mV for P3)

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SLIDE 37

Other Performance Metrics of P4

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SLIDE 38

Proposed P4 FE ASIC Baseline DC Variation in LN – MC simulations

100 run MC simulations (PV+MM) at schematic level Setting: BL = 200/900 mV, Gain = 14 mV/fC, Tp = 2 us, DC, Buffer not used, 500pA

1 11 8 14 17 20 16 9 3 1 5 10 15 20 25 180 190 200 210 220 230 240 250 260 270 280 More Frequency Bin (mV)

200 mV BL

5 15 24 21 22 10 3 5 10 15 20 25 30 900 910 920 930 940 950 960 970 980 990 1000 More Frequency Bin (mV)

900 mV BL

Mean (mV) 932.9

  • Std. dev. (mV)

14.29 Mean (mV) 227.4

  • Std. dev. (mV)

19.42

Slightly better than P3

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SLIDE 39

Simulated ENC of the proposed P4 channel

556.2 423.2 368.7 371.5 300 350 400 450 500 550 600 650 700 0.5 µs 1 µs 2 µs 3 µs

ENC (e-) for 900 mV BL

100 pA 500 pA 1 nA 5 nA 553.1 421.9 368.3 371 300 350 400 450 500 550 600 650 700 0.5 µs 1 µs 2 µs 3 µs

ENC (e-) for 200 mV BL

100 pA 500 pA 1 nA 5 nA

ENC almost similar to P3

Setting: BL = 200/900 mV, Gain = 14 mV/fC, Cdet = 150 pF

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SLIDE 40
  • 4.00E-04
  • 3.00E-04
  • 2.00E-04
  • 1.00E-04

0.00E+00 1.00E-04 2.00E-04 20 40 60 80 100 120 Residuals (V) Charge (fC)

Residual Plot

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 20 40 60 80 100 120 vOut (mV) Charge (fC)

Output voltage [mV] vs Input charge [fC] INL = ± 16.6 m% (Better than P3 and compatible with 12 bits)

Proposed P4 simulation results – Linearity

Setting: BL = 200 mV, Gain = 14 mV/fC, Tp = 2 us, 500pA, Cdet = 150 pF

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SLIDE 41

Single-ended to Differential Converter (SDC) buffer

  • Two options

1. Porting the SDC design present in cold ADC (65 nm) → Vdd = 2.25 V 2. Based on single-ended buffer core

  • Already present in 180 nm, highly linear and silicon-proven rail-to-rail operation
  • Need to modify for differential output and qualify with simulations
  • Addition of Common-Mode Feedback Circuit (CMFB)

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Single-ended Buffer

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SLIDE 42

LArASIC P4 estimated size

  • Differential buffers will reuse single-

ended buffer output and supply pads

  • Need 16 more output, 2 Vddo and 2

Vsso pads.

  • Pad count 100 (from 80)
  • Estimated layout size = 7 mm x 6.2 mm

(from 6.0 mm x 5.7 mm)

Moved from right side

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SLIDE 43

Summary and Future Work

  • Discussed existing P3 LArASIC
  • Simulations performed with foundry models
  • Unfortunately cold models don’t exist
  • Proposed P4 LArASIC with schematic modifications to mitigate
  • BGR problem – Done
  • Baseline DC shift variability – Done
  • Ledge effect – Done
  • To start work on layout and post-layout verifications – By end of March
  • Differential buffer – By end of April
  • All layout Modifications, extracted simulations and tapeout – End of June

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SLIDE 44

Backup Slides

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SLIDE 45

P3 Simula latio ion result lts – Linear arit ity testin ing g in time domai ain

Current entering the channel

Setting: BL = 200 mV, Gain = 14 mV/fC, Tp = 2 us, 500pA, Cdet = 150 pF

45