LArASIC - FE ASIC for DUNE LAr TPC Dr. Venkata Narasimha Manyam Instrumentation Division, Brookhaven National Laboratory February 6th, 2020, CERN
Outline • LArASIC Introduction • Changes Between Recent LArASIC Versions • LArASIC P3 Simulations and Identified Issues • LArASIC P4 Development • LArASIC P4 Simulations • Summary and Future Work 2
LArASIC – Simplified block diagram & functionality • 16 channels • Two-stage charge amplifier, high-order filter (5 th ) • Adjustable Reset Quiescent Current (RQI/leakage) settings (100 pA, 500 pA, 1nA, 5 nA) • Adjustable gain: 4.7, 7.8, 14, 25 mV/fC (Max. charge 55, 100, 180, 300 fC) • Adjustable filter time constant (peaking time 0.5, 1, 2, 3 µs) • Selectable collection/non-collection mode (baseline 200, 900 mV) • Selectable DC/AC coupling (100µs HPF time-const.) • Rail-to-rail analog signal processing with single-ended buffer • Bandgap referenced (BGR) biasing circuits • Temperature sensor (~ 3mV/°C) • Integrated 6-bit pulse generator • 144 configuration registers, SPI interface • 5.5 mW/channel (input MOSFET 3.9 mW) • ~ 16,000 MOSFETs • Designed for room (300K) and cryogenic (77K) operation • Technology CMOS 0.18 µm, 1.8 V, 6M, MIM, SBRES 3
Previous FE ASIC layout Successful deployment with 5.7 mm excellent performance at MicroBooNEand ProtoDUNE *P2 AISC 6.0 mm 4
LArASIC Channel – Simplified block diagram Charge Amplifier Shaper AC/DC Buffer Adaptive Continuous Reset (ACR) RQI/leakage 5
Changes between recent versions of the FE ASIC P1 (V6) P3 (V8) P2 (V7) • PA-SH changed to correct return to • 6-bit pulse generator added • Geometric dependence for 200 mV baseline issue baseline mitigated by replacing • SLKH, i.e., high (10x) Reset-loop • Removed RQI subtraction in CA2 current biasing with voltage in shaper Quiescent Current (RQI) added to 1 st and 2 nd stages → changes CA2 bias • Changed W and L in the ACR of CA1 compensate for saturation effects vol. and CA2 (aka “Chirping”) • Ledge behavior still present in cold • {W,L} in ACR CA2, P2 = {8*W, • BGR fix didn’t work → 7% chips 8*L} ACR CA2, P1 • BGR issue of 7% chips in cold still don’t start in cold • Inter-channel BL variation present • RQI subtraction added in CA2 to (geometric dependence) for 200 correct for BL DC for 5nA RQI → CA2 mV BL option observed due to packaging stress Adaptive Continuous Reset (ACR) non- functional → needs 1GOhm at • Ledge observed only in cold during input shower event (after P3 tape-out) • Transistor sizing similar to V5 • BGR issue of 7% chips in cold still present • Imperfect PZ cancellation → return to baseline issues 6
Outline of Identified problems and simulation methodology • Identified problems • Bandgap Voltage Reference (BGR) fails in 7% of the chips Only in Cold • Ledge effect during shower event operation • Simulation procedure • Model files from foundry used • “cmno18_asp_v1d2.scs” in BSIM4 (V4.5) • Extrapolated for LN and LAr temperatures, outside of guaranteed range • Mismatch models only for MOSFETs • Perform different analysis needed such as DC, AC, stability (STB), noise , transient (with or/and without noise) in nominal, process corners (SS, FF, SF and FS) and Monte Carlo with process variation (PV) and mismatch (MM) • Schematic level simulations have been shown later 7
BGR Problem in P3 8
Bias module based on Bandgap Voltage Reference (BGR) • Still 7% of the P3 chips doesn’t start only in cold → They are currently screened -off Bias module BGR 9
P3 BGR simulations 50 run MonteCarlo(PV+MM) sim.s with Temp. sweep -196 to 125 ° C 4 runs out of 50 show problem at cold 1 (33) 2(36,32) 1 (43) Expected ~ 1.2 V 10
Start-up sim.s of P3 BGR 2 runs (21, 43) out of 50 show problem at cold by settling to ~ supply (1.775 V) 1µs supply ramping; 50 run MC (PV+MM) at LAr and RT 11
Ledge Effect in P3 12
Ledge effect in LArASIC P3 • Only during cold operation and mostly with shower charge (e.g. > 100 fC for 14 mV/fC setting) for 200 mV baseline setting, LArASIC P2 and P3 outputs of some of the channels saturate and produce ledge characteristic after a delay Image from: Study of the “Ledge” effect in protoDUNE readout, Hucheng Chen, et al. 13
Simulation of shower event at LN : 500 fC input for 50 µs Ledge effect only observed with new models (BSIM4) and not with old (BSIM3) LArASIC V5 (V4*) LArASIC P3 Red: old model tPeak = 1 µs Yellow: new model Leakage = 500 pA BL = 200 mV No ledge effect with Gain = 14 mv/fC old and new models Cdet = 150 pF 50 µs 50 µs TT_m196 → rf018.scs is BSIM3 (V3.24) ~17k lines 180 nm TSMC tech. model files TT_new_m196 → cmno18_asp_v1d2.scs is BSIM4 (V4.5) ~38k lines 14
Origin of ledge effect • Adaptive Continuous Reset(ACR) network in the ca2n resized from V5(V4*)/V6(P1) moving to V7(P2)/V8(P3) to improve pole-zero cancellation (baseline restoration) • Width and Length of the transistors in ACR increased by 8 times in P3 compared to V5, increased gate cap. by ~64 times, making the loop unstable, causing ledge Ledge effect origin fully understood Both W and L increased by 8 times 15
Other Performance Metrics of P3 16
Simulations of P3 channel baseline DC shift for different settings * Setting : BL = 200/900 mV, Gain = 14 mV/fC, Cdet = 150 pF Baseline DC (V) for 200 mV BL Baseline DC (V) for 900 mV BL 0.700 1.400 0.600 1.300 0.500 1.200 0.400 1.100 0.300 1.000 0.258 0.959 0.947 0.245 0.233 0.934 0.927 0.200 0.900 0.226 0.100 0.800 Δ V = 32 mV Δ V = 32 mV 0.000 0.700 0.5 µs 1 µs 2 µs 3 µs 0.5 µs 1 µs 2 µs 3 µs 100 pA 500 pA 1 nA 5 nA 100 pA 500 pA 1 nA 5 nA RQI (leakage) setting of 500 pA mostly used and 5 nA is not needed Baseline shift reduces signal swings 17
P3 ASIC baseline DC variation in LN – Measurement of 171 chips, 2736 channels Setting : BL = 200/900 mV, Gain = 14 mV/fC, Tp = 2 us, DC, Buffer on, 500pA. 1.6% had unresponsive channels and 4.79% did not respond after a power cycle in LN 900 mV BL 200 mV BL 800 900 857 733 Mean (mV) 243.78 Mean (mV) 898.88 814 Std. dev. (mV) 15.95 800 Std. dev. (mV) 12.87 700 700 600 546 546 600 500 513 Frequency Frequency 500 400 360 401 400 308 300 300 200 160 200 132 88 100 77 100 40 20 10 9 6 4 4 2 1 1 0 0 0 850 860 870 880 890 900 910 920 930 940 950 More 200 210 220 230 240 250 260 270 280 290 300 More Bin (mV) Bin (mV) 18
P3 FE ASIC baseline DC variation in LN – MC simulations 100 run MC simulations (PV+MM) at schematic level Setting : BL = 200/900 mV, Gain = 14 mV/fC, Tp = 2 us, DC coupling, Buffer not used, 500pA, Cdet = 150 pF Bandgap reference voltage problem (1.78 V instead of 1.2 V) in 6% (200 mV BL) and 4% (900 mV BL) simulation runs 200 mV BL 900 mV BL Mean (mV) 245.1 Mean (mV) 945.8 Std. dev. (mV) 20.23 Std. dev. (mV) 14.52 25 30 23 25 25 20 22 20 17 15 14 14 Frequency Frequency 12 14 15 11 10 10 10 7 5 5 4 5 3 3 3 1 1 1 0 0 0 0 200 210 220 230 240 250 260 270 280 290 300 900 910 920 930 940 950 960 970 980 990 Bin (mV) Bin (mV) Close to measurements 19
Simulations of P3 channel ENC Setting : BL = 200/900 mV, Gain = 14 mV/fC, Cdet = 150 pF ENC (e-) for 200 mV BL ENC (e-) for 900 mV BL 800 800 700 700 600 600 557.8 555.6 500 500 423.7 424.7 400 400 372.4 372.5 369.8 369.6 300 300 200 200 100 100 0 0 0.5 µs 1 µs 2 µs 3 µs 0.5 µs 1 µs 2 µs 3 µs 100 pA 500 pA 1 nA 5 nA 100 pA 500 pA 1 nA 5 nA 20
P3 Simulation results – Linearity Setting : BL = 200 mV, Gain = 14 mV/fC, Tp = 2 us, 500pA, Cdet = 150 pF Output voltage vs Input charge Residual Plot 1.6 3.00E-04 1.4 2.00E-04 1.2 1.00E-04 1.0 0.00E+00 vOut (V) 0 20 40 60 80 100 120 Residuals (V) 0.8 -1.00E-04 0.6 -2.00E-04 0.4 -3.00E-04 INL = ± 23 m% < |0.07|% for full range 0.2 -4.00E-04 (Compatible with 12 bits) 0.0 0 20 40 60 80 100 120 -5.00E-04 Charge (fC) Charge (fC) 21
Single-ended output buffer linearity Output voltage vs Input voltage Residual Plot 1.8 2.50E-07 1.6 2.00E-07 1.4 1.50E-07 1.2 1.00E-07 1 vOut (V) Residuals (V) 5.00E-08 0.8 0.00E+00 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0.6 -5.00E-08 0.4 -1.00E-07 0.2 -1.50E-07 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 -2.00E-07 vIn (V) vIn (V) INL = ± 14 µ% (Typical) 22
LArASIC P4 Development - Towards a robust design 23
Required Improvements for New FE ASIC (P4) • Required • Address bandgap voltage reference failures happening in ~7% of the chips at cold • Ledge effect mitigation during shower events up to 500 fC input charge • Implement single ended to differential buffer matching with ADC spec.s • Additional • Decreasing baseline shift for different settings 24
BGR Problem Mitigation in P4 25
Mitigation of Bandgap Reference problem with schematic modifications for P4 In all the previous versions of BGR, bias of BGR was derived from BGR → Problem We decoupled it 26
50 run MC (PV+MM) sim.s with Temp. sweep -196 to 125 ° C of proposed BGR All 50 runs pass 27
Start-up sim.s of proposed BGR with 1µs supply ramping; 10 run MC (PV+MM) at LAr and RT 10 runs with different noise seed in transient noise for each MC run All 200 runs (100 LAr and 100 RT) pass 28
Recommend
More recommend
