ATMEL FPGA User Group WORKSHOP Astrium F feedback on the ATF280 - - PowerPoint PPT Presentation

ATMEL FPGA User Group WORKSHOP Astrium F feedback on the ATF280

part of CNES study “In-flight reconfiguration of FPGA” n°R-S08/TG-0002-034

Florent MERLAY – ASE3

This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed.

Atmel FPGA User Group Workshop - ESTEC 2010/03/03

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Summary

• Context
• In-flight reconfigurations of FPGA : use and types
• Design rules for reconfigurable units
• Reconfigurations using ATF280E
• Test design and procedure
• Questions

This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed.

Atmel FPGA User Group Workshop - ESTEC 2010/03/03

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Context

This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed.

Atmel FPGA User Group Workshop - ESTEC 2010/03/03

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Context

• This work is part of the CNES

«In-flight reconfiguration of FPGA» R&D study

• The responsible at CNES is Jean BERTRAND
• This contract is managed by Astrium F Elancourt

with the contribution of Astrium F Toulouse for system maters

• This R&D study is divided in 2 parts :
• part 1 : Theoretical study
• part 2 : Mock-up

This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed.

Atmel FPGA User Group Workshop - ESTEC 2010/03/03

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Content of the study

• The theoretical study (part 1) deals with:
• the study of reconfiguration features offered and constraints imposed by reconfigurable FPGAs
• the evaluation of software allowing the reconfiguration of eligible FPGAs

and the definition of a partial reconfiguration flow for each one

• the definition of design rules for reconfigurable systems meant to be embedded in FPGAs
• the study of system/board architectures allowing reconfiguration
• the study of impacts on the embedded software of the introduction of reconfigurability
• Part 2 aims at designing a demonstrator and providing a test report
• This presentation only features part of the theoretical study

Part 1 report is available from CNES on demand

This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed.

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• Focus has been put on rad-hard reconfigurable FPGAs

2 eligible components : the SIRF (Xilinx) & the ATF280 (Atmel)

Dealing with radiations adds many constraints which interfere with the primary objective

• Reconfiguration capabilities of both FPGAs have equally been studied
• Xilinx benefits from its on-ground experience of reconfiguration

The SIRF offers an internal reconfiguration interface and dedicated options A PlanAhead add-on can be used to generate partial reconfiguration bitstreams As it is radiation hardened, the FPGA is obviously ITAR

• Atmel offers a FPGA with equal reconfiguration capabilities but no dedicated software

The FPGA is non-ITAR

• ATF280 has been chosen over the SIRF for mock-up

in order to address the growing demand of non-ITAR FPGA while proving the reconfiguration capabilities of the ATF280

Eligible FPGAs & Trade-off

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Atmel FPGA User Group Workshop - ESTEC 2010/03/03

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In-flight reconfigurations of FPGA Use & types

This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed.

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• Late design modifications

The increasing computational power required by data-processing payloads can no longer be solely addressed by software algorithms. Part of the data-processing is thus performed using hardware: ASICs. Due to long manufacturing delay, ASICs must be designed early on in projects.  replacing some of them with reconfigurable FPGAs would allow late modifications

• Experimental satellites

Using reconfigurable FPGAs in experimental satellites payloads would allow operators to adapt data-processing to mission updates as well as enable the use of new algorithms

• Telecommunication satellites

SatCom satellites being designed for longer and longer missions (up to 18 years for the current generation), it’s getting useful to anticipate the periodical obsolescence of data transmission standards by allowing the update of components in charge of these functionalities

Use of in-flight reconfigurations

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• Static reconfiguration

Implemented function inhibited during the reconfiguration

• Total: configuration memory either fully overwritten or erased then rewritten

 can be used to fix bugs, update algorithms, …

• Partial: configuration memory partially overwritten

 can be used to swap one of the implemented functions

• Dynamic partial reconfiguration

Part of the implemented functionality remains active

 can be used to swap one of the implemented functions

without having to put the whole design on hold

In-flight reconfiguration types

This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed.

Atmel FPGA User Group Workshop - ESTEC 2010/03/03

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Design rules for reconfigurable units

This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed.

Atmel FPGA User Group Workshop - ESTEC 2010/03/03

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The array section holding the dynamic entity

• is in an unstable state during reconfigurations:

Values of peripheral signals used as inputs by the rest of the design can change due to routing modification

• comes out in an undefined state at the end of reconfigurations:

Values of peripheral signals used as outputs by the rest of the design are likely to be used to change flip-flop states

Flip-flops aren’t reset by reconfiguration and consequently remain in the state

they were in before that operation

 ensure that the reconfigured entity comes out of reconfigurations in a predictable state and doesn’t prevent the rest of the design from running normally during the reconfiguration

Disturbance created by reconfiguration

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• Predictable state after reconfiguration  Reset
• Static reconfiguration

Whole design must be reset  no specific impact

• Dynamic reconfiguration

Whole design can’t be reset

 dedicated reset logic must be added to the static entity and enabled during the reconfiguration

Deducted design constraints

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• Problem: reconfiguring the dynamic entity can disturb the static entity
• Directly: uncontrolled dynamic entity outputs can trigger events

i.e.: unwanted AHB bus requests, interrupts, …

• Indirectly: dynamic entity unavailable

The static entity requires that the dynamic entity performs operations it cannot perform, being reconfigured i.e.: watchdog put on hold

• Suggested solution: replace the dynamic entity during reconfiguration

Deducted design constraints

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• Example : 1553 Bus controller

Triggers all transfers performed on the bus

TX/TXB output signals kept in Idle state during reconfiguration

• Well fitted interfaces
• Master interfaces (i.e.: AHB master, 1553 bus controller, …)

The most adapted to reconfiguration  their outputs shall be kept in an Idle state during reconfiguration

• Slave interfaces not used during reconfiguration

As adapted as master interfaces  their outputs shall be kept in a state that makes them transparent

• Slave interfaces likely to be used during reconfiguration
• With delayed/error answer capability: rather complex maintenance module
• Without: shouldn’t be reconfigured

Deducted design constraints

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Reconfiguration using ATF280E

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• ATF280 Configuration states
• Power-on reset : configuration memory erasure at Power-on
• Manual reset : triggered configuration memory erasure
• Configuration download : data loaded in the configuration memory
• Idle : no configuration activity
• ATF280 Configuration modes
• Master : auto-configuration after power-on and when triggered
• Slave : configuration handled by other device
• Synchronous RAM : configuration performed loading data

into the device as though it were a SRAM

ATF280 configuration states and modes

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• Configuration options and CR register
• I/O : can all be tristated either by asserting OTS or setting CR31
• Reset : flip-flops can be reset by setting CR30
• Clocks : can be deactivated independently by setting CR27-16
• CHECK function : can be used without asserting CHECK input
• Master mode reconfiguration : last address provided to the component

can be saved so that a different bitstream can be used for the next configuration

ATF280 configuration options

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Atmel FPGA User Group Workshop - ESTEC 2010/03/03

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• Precision Synthesis
• Create a project : name, target FPGA, max running frequency
• Define the design : edit or/and import VHDL/Verilog files then add constraints
• Compile
• Synthesize
• Figaro IDS
• Create a project : import synthesized top level
• Define timing and I/O allocation constraints
• Automatic place & route
• Generate bitstream
• Configurator
• Create EEPROM init file
• In-situ programming of FPGA EEPROM

ATF280 regular design flow

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Atmel FPGA User Group Workshop - ESTEC 2010/03/03

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• Although ATF280E can be partially reconfigured, there is no

defined flow for the generation of partial reconfiguration bitstreams

• Such bitstreams can be generated anyway
• thanks to the fact that incremental routing can be performed
• through the use of a trick : closing the Figaro and replacing one entity with another
• by differentiating bitstreams
• Partial reconfiguration flow defined on the next slide must be

followed carefully

ATF280 partial reconfiguration flow

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Atmel FPGA User Group Workshop - ESTEC 2010/03/03

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• Design description
• Static and dynamic entities instanced separately at top level
• Synthesis
• Top level synthesized with a black box instead of the dynamic entity

Insert I/O pads

• Different version of the dynamic entity synthesized separately

Do not insert I/O pads

• Place & route
• Import dynamic entity as macro, place & locally route then save in library
• Set library, import static entity, place & route then generate bitstream
• Save, replace library and do over (static entity routing locked)
• Compress then manually edit difference bitstreams

ATF280 partial reconfiguration flow

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Atmel FPGA User Group Workshop - ESTEC 2010/03/03

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• Example of placed and locally routed macro

ATF280 partial reconfiguration flow

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Atmel FPGA User Group Workshop - ESTEC 2010/03/03

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• Placed and routed complete design : first dynamic entity

ATF280 partial reconfiguration flow

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Atmel FPGA User Group Workshop - ESTEC 2010/03/03

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• Placed and routed complete design : replaced dynamic entity

ATF280 partial reconfiguration flow

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Atmel FPGA User Group Workshop - ESTEC 2010/03/03

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• Encountered issues (rather simple test design : 5% of the resources)
• Hard-macros

Cell placement unfitted for insertion into higher level design I/Os placed within the dedicated placement area, not at periphery can be manually placed at periphery but this creates routing problems Outputs cannot be static Problem can be solved redefining constant signals as flip-flop outputs

• Routing

Troubles often encountered routing the design with an implemented macro Routing the 2nd version of a design has never been possible

• Inability to reserve space for the dynamic module

The larger version must consequently be used for the 1st place & route  rather unfitted to bug fixing or functionality improvement/extension

ATF280 partial reconfiguration flow

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Atmel FPGA User Group Workshop - ESTEC 2010/03/03

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• Procedure and constraints

ATF280 reconfigurations

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Atmel FPGA User Group Workshop - ESTEC 2010/03/03

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Practical evaluation of ATF280 reconfiguration

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• Dynamic entity used to decrypt data

provided over an UART interface and temporarily stored in SDRAM

• Messages retrieved in SDRAM

displayed on the LCD before, during and after the reconfiguration

• Operations triggered by user through

the use of the second UART interface

• Decrypted data displayed on PC screen

Proposed test design

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• Setup

Text cut in 2 halves : 1st half encrypted using 3DES format, 2nd half encrypted using TwoFish Not encrypted text transmitted and stored in the SDRAM, displaying triggered Data to be displayed on the LCD defined  2 texts and data to be displayed transmitted to the FPGA and stored in the SDRAM

• 3DES decryption

3DES decryption of encrypted text performed by dynamic entity Decrypted text transmitted to the PC and displayed on screen

• Reconfiguration

Not encrypted text transmitted to the PC Reconfiguration performed using the PC

• TwoFish decryption

TwoFish decryption of encrypted text performed by dynamic entity Decrypted text transmitted to the PC and displayed on screen

Proposed test procedure

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• Although it has successfully been performed on AT40K,

reconfiguration has never been performed on ATF280

• Software routing issues will have to be by-passed

Foreseen difficulties

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• The theoretical study has shown that the 2 eligible FPGAs can be reconfigured

totally and partially, either in a static or a dynamic way, provided that certain design rules are respected

• ATF280 should not only be regarded as a non-ITAR alternative to antifuse

FPGAs, it can be used to design innovative data computing systems …

• Reconfigurability can be eased by
• incorporating in Figaro
• the library swap “trick”
• a bitstream difference tool
• improving routing algorithms
• The study is currently on hold, Atmel being temporarily unable to deliver

Precision licenses for ATF280 synthesis It will last 5 more months

Conclusion

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Questions