A Low-Power MTJ-Based Nonvolatile FPGA Using Self-Terminated - - PowerPoint PPT Presentation

2016/9/20 1 FPL2016 (S4b)

26th International Conference on Field-Programmable Logic and Applications 29th August – 2nd September, 2016, Lausanne, Switzerland

A Low-Power MTJ-Based Nonvolatile FPGA Using Self-Terminated Logic-In-Memory Structure

Session S4b 31st August 10:30-12:35 Daisuke Suzuki1 and Takahiro Hanyu2

1Frontier Research Institute for Interdisciplinary Sciences, Tohoku University, JAPAN

http://www.fris.tohoku.ac.jp/fris/index.html

2 Laboratory for Brainware Systems, Tohoku University, JAPAN

http://www.ngc.riec.tohoku.ac.jp [Acknowledgement] This research is supported by JSPS KAKENHI Grant Number 25870067. A part of this research is supported by CIES consortium program.

Background

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How to overcome standby power problem of FPGA?

A large number of HW components are embedded for reconfigurability ⇒ Low area & energy efficiency

[Ref.] E. Pop, Nano Res. 3 (2010) 147.

Power density [W/cm2] CMOS Technology [nm]

101 10-1 10-2 103 102 101

Active Standby

Large amount of standby power due to nano-scale CMOS process  FPGA (Field-Programmable Gate Array)

→ Various digital systems are implemented with short design time and low cost.

[Ref.] Y. Liu, et al., ISSCC, pp. 84-85, Feb. 2016.

MTJ Device

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• High endurance
• Scalability
• CMOS compatibility
• 3D-stacking

RP (Low res.) RAP (High res.) Storage element SRAM ReRAM device Atom switch CAAC- IGZO MTJ device Nonvolatile No Yes Yes Yes Yes Scalability + ++ ++

• ++

Endurance ++

• +

++ Write access ++ +

• +

++

MTJ device is the best candidate for realizing nonvolatile logic.

MTJ-Based Nonvolatile Logic Families

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MRAM

MTJ device is the best candidate for realizing Nonvolatile logic LSI.

• T. Ohsawa, et al., VLSIC, 2013. S. Matsunaga, et al., VLSIC, 2013. N. Sakimura, et al., ISSCC, 2014.
• D. Suzuki, et al., VLSIC, 2015.

JSPS FIRST program (Leader Prof. H. Ohno)

Si SRAM Logic FF Logic FF

1st Generation 2nd Generation

Si SRAM LIM Storage elements are replaced by nonvolatile ones. Storage and logic functions are merged. → Logic-in-memory (LIM) structure

MTJ MTJ MTJ MTJ

LIM

MTJ MTJ

Design Issue

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Logic Element (LE)

Lookup table (LUT) FF MUX X D Z SEL n

Routing switch

Latch p-MTJ device

CLB: Configurable logic block CB: Connection block SB: Switch block CFGC: Configuration circuit

CLB CB SB CB CFGC Configuration data

Tile

1. Reduction of the overhead due to recall/backup operations 2. Reduction of the number of leakage current paths

Power Time Dynamic Static (Power off) Static (Power on) Recall Backup

Logic-In-Memory Structure

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Proposed

64 SA: Sense amplifier WT: Write transistor NMOS multiplexer tree X D Buffer 64 6

Nonvolatile SRAM based

D SA/buffer (shared) 64-bit nonvolatile SRAM MTJ0 WT SA MTJ1 WT SA MTJ6 3 WT SA MTJ configuration array MTJ0 WT MTJ1 WT MTJ6 3 WT WT (shared)

Compact circuitry with small number of leakage current paths

Leakage path

Both SAs and WDs are shared. VD

D

VDD

NMOS multiplexer tree X 6

VD

D

Self-Terminated Power-Gating Scheme

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Time ITOTAL

t1 t0 t2 tWORST w/o self- termination

FF[1] Done FF[0] Done FF[2] Done

IB[1] IL IB[0] IB[2]

F[0] VDD PGEN GND N0 F[1] F[2] SLP PGEN GND VDD N1 N2

VDD

FF0 F[0] FF1 FF2

Minimization of both backup energy and leakage energy.

PG controller

F[1] F[2] Power switch

Evaluation

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5 10 15 20 25 30 alu4 apex2 apex4 bigkey clma des diffeq dsip elliptic ex1010 ex5p frisc misex3 pdc s298 s38417 s38584.1 seq spla tseng Average

SRAM-based NVSRAM based Proposed

Total power [mW]

Frequency: 100 MHz α: 20% Tc: 5 µs tR: 2 ns SRAM-based NVSRAM based Proposed Average total power

19.8mW 3.12 mW 1.97 mW

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Thank you!