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1 ZELE EE618 LECTURE 20 12 OCT 2018 2 ZELE EE618 L-20 3 - - PDF document
1 ZELE EE618 LECTURE 20 12 OCT 2018 2 ZELE EE618 L-20 3 - - PDF document
1 ZELE EE618 LECTURE 20 12 OCT 2018 2 ZELE EE618 L-20 3 ZELE EE618 L-20 4 ZELE EE618 L-20 5 ZELE EE618 L-20 6 ZELE EE618 L-20 7 ZELE EE618 L-20 8 ZELE EE618 L-20 9 ZELE EE618 L-20 10 ZELE EE618 L-20 11 ZELE
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Sample of Design Rules provided by the foundry
(Below shown rules doesn’t correspond to SCL process) MIM Capacitor Top plate connected to M6 M5 acts as botuom plate Dielectric thickness = 56nm
Interconnect layers (Doesn’t correspond to SCL process)
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Basic Layers in SCL 180nm Difgerent ways of forming Diode Difgerent ways of forming BJT
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Contacts to regions
Top View of NMOS Cross sectjonal view of NMOS Top View of PMOS Cross sectjonal view of PMOS
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NMOS Total width = (0.5um) x 2 fjngers = 1um Length= 0.18 um NMOS Total width = (0.5um) x 2 multjples = 1um Length= 0.18 um
Difgusion resistors
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Poly resistors
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Mk-1 Mk MOM Capacitors
htups://web.stanford.edu/class/ee311/NOTES/Interconnect_Al.pdf
Electromigratjon failure
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