CMOS Analog VLSI Design Course Code: EE618 Department: Electrical - PowerPoint PPT Presentation

CMOS Analog VLSI Design Course Code: EE618 Department: Electrical Engineering Semester: Autumn 2015 Date: July 21, 2015 Instructor: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1

4 Basic Definitions Related to Energy Band Diagram of Materials • Vacuum level: Energy state (energy level) of electrons outside the material (E 0 ) • E c : Lowest energy level corresponding to the conduction band • E v : Highest energy level corresponding to the valence band • Electron affinity: The difference between E 0 and E c IIT-Bombay Lecture 2 M. Shojaei Baghini

5 MOS Capacitor Structure, Flat-band Condition V FB = ψ g - ψ s (gate and Source: Modern Semiconductor Devices for semiconductor Integrated Circuits by work functions) Chenming C. Hu, 2010 Ex.: V FB = 4.05 -(4.05 + (E c -E f )/q) ≈ -0.7V IIT-Bombay Lecture 2 M. Shojaei Baghini

6 MOS Capacitor Structure, Surface Depletion Source: Modern Semiconductor Devices for Integrated Circuits by Chenming C. Hu, 2010 IIT-Bombay Lecture 2 M. Shojaei Baghini

MOS Capacitor Structure, Surface Inversion 7 2 SiO = ⇒ ≈ µ Assumptions: t 5 nm C 6 . 9 fF / m ( ) ox ox 2 • P-ype substrate N c =N v for simplicity • Q = Φ + Φ − dep 2 V TH gs B C ox Q Q = Φ + Φ − − dep inv V 2 gs gs B C C ox ox Q ≈ − inv V TH C ox   KT N   Φ = − sub ln : ( p sub )   B   q n i = − ε × Φ Q 2 q 2 N dep si B sub Source: Modern Semiconductor Devices for Integrated Circuits by C. C. Hu, 2010 IIT-Bombay Lecture 2 M. Shojaei Baghini

8 Plots of Calculated Threshold Voltage Source: Modern Semiconductor Devices for Integrated Circuits by C. C. Hu, 2010 IIT-Bombay Lecture 2 M. Shojaei Baghini

9 MOS Transistor IIT-Bombay Lecture 2 M. Shojaei Baghini

10 Body Bias Effect ( ) Q = Φ + Φ − + γ Φ + − Φ dep 1 V 2 2 V 2 TH MS B B SB B C ox   KT N   Φ = sub ln   B   q n i Effect of extra charge in the depletion region = − ε × Φ Q 2 q 2 N dep si F sub ε 2 q N γ = si sub C ox IIT-Bombay Lecture 2 M. Shojaei Baghini

11 DC I-V Characteristics = − Q WC ( V V ) ch ox GS TH Charge per unit length in the channel = − − Q WC ( V V ( x ) V ) ch ox GS TH = − − − I WC ( V V ( x ) V ) v D ox GS TH dV ( x ) = − − µ ( ( ) ) I WC V V x V D ox GS TH n dx Ref.: Design of analog CMOS integrated circuits by Behzad Razavi IIT-Bombay Lecture 2 M. Shojaei Baghini

12 DC I-V Characteristics (cont’d) V L = ∫ DS ∫ µ − − I dx WC ( V V ( x ) V ) dV D ox n GS TH = = x 0 V 0   W ( ) 1 1 W ( ) = µ − − ⇒ = µ − 2 2 I C V V V V I C V V   D n ox GS TH DS DS D . max n ox GS TH   L 2 2 L Ref.: Design of analog CMOS integrated circuits by Behzad Razavi IIT-Bombay Lecture 2 M. Shojaei Baghini