CMOS Analog VLSI Design Course Code: EE618 Department: Electrical - - PowerPoint PPT Presentation

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CMOS Analog VLSI Design Course Code: EE618 Department: Electrical - - PowerPoint PPT Presentation

Aug 08, 2023 183 likes •296 views

CMOS Analog VLSI Design Course Code: EE618 Department: Electrical Engineering Semester: Autumn 2015 Date: July 21, 2015 Instructor: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 4 Basic Definitions Related to Energy Band Diagram

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CMOS Analog VLSI Design Course Code: EE618 Department: Electrical Engineering

Semester: Autumn 2015 Date: July 21, 2015 Instructor: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in

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IIT-Bombay Lecture 2 M. Shojaei Baghini

Basic Definitions Related to Energy Band Diagram of Materials

  • Vacuum level: Energy state (energy level) of

electrons outside the material (E0)

  • Ec: Lowest energy level corresponding to the

conduction band

  • Ev: Highest energy level corresponding to the

valence band

  • Electron affinity: The difference between E0 and Ec
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IIT-Bombay Lecture 2 M. Shojaei Baghini

MOS Capacitor Structure, Flat-band Condition

Source: Modern Semiconductor Devices for Integrated Circuits by Chenming C. Hu, 2010

VFB = ψg - ψs (gate and semiconductor work functions) Ex.: VFB = 4.05 -(4.05 + (Ec-Ef)/q) ≈ -0.7V

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IIT-Bombay Lecture 2 M. Shojaei Baghini

MOS Capacitor Structure, Surface Depletion

Source: Modern Semiconductor Devices for Integrated Circuits by Chenming C. Hu, 2010

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IIT-Bombay Lecture 2 M. Shojaei Baghini

MOS Capacitor Structure, Surface Inversion

Source: Modern Semiconductor Devices for Integrated Circuits by C. C. Hu, 2010

Assumptions:

  • P-ype substrate
  • Nc=Nv for simplicity

sub B si dep i sub B

  • x

inv TH

  • x

inv

  • x

dep B gs gs

  • x

dep B gs TH

N q Q sub p n N q KT C Q V C Q C Q V C Q V Φ × − = −         = Φ − ≈ − − Φ + Φ = − Φ + Φ = 2 2 ) ( : ln 2 2 ε

) ( / 9 . 6 5

2 2 SiO

m fF C nm t

  • x
  • x

µ ≈ ⇒ =

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IIT-Bombay Lecture 2 M. Shojaei Baghini

Plots of Calculated Threshold Voltage

Source: Modern Semiconductor Devices for Integrated Circuits by C. C. Hu, 2010

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IIT-Bombay Lecture 2 M. Shojaei Baghini

MOS Transistor

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IIT-Bombay Lecture 2 M. Shojaei Baghini

Body Bias Effect

( )

  • x

sub si sub F si dep i sub B B SB B

  • x

dep B MS TH

C N q N q Q n N q KT V C Q V ε γ ε γ 2 2 2 ln 2 2 2

1

= Φ × − =         = Φ Φ − + Φ + − Φ + Φ =

Effect of extra charge in the depletion region

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IIT-Bombay Lecture 2 M. Shojaei Baghini

DC I-V Characteristics

Ref.: Design of analog CMOS integrated circuits by Behzad Razavi

) (

TH GS

  • x

ch

V V WC Q − =

Charge per unit length in the channel

) ) ( (

TH GS

  • x

ch

V x V V WC Q − − =

v V x V V WC I

TH GS

  • x

D

) ) ( ( − − − =

dx x dV V x V V WC I

n TH GS

  • x

D

) ( ) ) ( ( µ − − =

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IIT-Bombay Lecture 2 M. Shojaei Baghini

DC I-V Characteristics (cont’d)

Ref.: Design of analog CMOS integrated circuits by Behzad Razavi

dV V x V V WC dx I

TH GS V V n

  • x

L x D

DS

) ) ( ( − − = ∫

∫

= =

µ

( ) ( )

2 max . 2

2 1 2 1

TH GS

  • x

n D DS DS TH GS

  • x

n D

V V L W C I V V V V L W C I − = ⇒       − − = µ µ