CMOS Analog VLSI Design Course Code: EE618 Department: Electrical - - PowerPoint PPT Presentation

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CMOS Analog VLSI Design Course Code: EE618 Department: Electrical - - PowerPoint PPT Presentation

Oct 04, 2023 117 likes •243 views

CMOS Analog VLSI Design Course Code: EE618 Department: Electrical Engineering Semester: Autumn 2015 Date: July 20, 2015 Instructor: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 What is called an analog element? Why are analog

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CMOS Analog VLSI Design Course Code: EE618 Department: Electrical Engineering

Semester: Autumn 2015 Date: July 20, 2015 Instructor: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in

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IIT-Bombay Lecture 1 M. Shojaei Baghini

What is called an analog element? Why are analog integrated circuits required?

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IIT-Bombay Lecture 1 M. Shojaei Baghini

Content of the course

  • Introduction
  • A review of MOS devices
  • Biasing concept in analog circuits
  • Basic single-stage and single-input analog modules
  • Differential amplifiers
  • Frequency response of basic analog modules
  • Feedback theory in analog circuits
  • Operational amplifiers
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IIT-Bombay Lecture 1 M. Shojaei Baghini

Content of the course (cont’d)

  • Reference generators
  • Noise
  • Output stages
  • Comparators
  • Basic considerations in the layout of analog circuits
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IIT-Bombay Lecture 1 M. Shojaei Baghini

Course References

  • Design and Analysis of Integrated Circuits by Paul
  • R. Gray and Meyer, 2009 (main reference 1)
  • Design of Analog CMOS Integrated Circuits by

Behzad Razavi, McGraw Hill, 2001 edition

  • nwards (main reference 2)
  • CMOS Analog Circuit Design by P. E. Allen et al. ,

Oxford University Press, 2002 edition onwards.

  • CMOS circuit design, layout and simulation, by R.
  • J. Baker, IEEE press, 2010.
  • We may use a paper for the course project
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IIT-Bombay Lecture 1 M. Shojaei Baghini

Grading

  • Quiz : (2 quizzes) 10%
  • Assignments (3): 15% (no late submission!)
  • Course Project: 15% (no late submission!)
  • Midsem Exam: 30% (20%)
  • Final Exam: 30% (40%)
  • EDA tools:
  • NGSPICE for circuit simulations
  • XCircuit for the schematic capture
  • Technology: 180nm CMOS process (test BSIM3 Version

3.1 model parameters available from MOSIS) BSIM stands for Berkeley Short-channel IGFET Model.

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IIT-Bombay Lecture 1 M. Shojaei Baghini

Notations for Signals

  • DC Bias values of the signals
  • Average value of a signal
  • Large signal
  • Small signal
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IIT-Bombay Lecture 1 M. Shojaei Baghini

Basic Definitions Related to Energy Band Diagram of Materials

  • Vacuum level: Energy state (energy level) of

electrons outside the material (E0)

  • Ec: Lowest energy level corresponding to the

conduction band

  • Ev: Highest energy level corresponding to the

valence band

  • Electron affinity: The difference between E0 and Ec
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IIT-Bombay Lecture 1 M. Shojaei Baghini

MOS Capacitor Structure, Flat-band Condition

Source: Modern Semiconductor Devices for Integrated Circuits by Chenming C. Hu, 2010

VFB = ψg - ψs (gate and semiconductor work functions) Ex.: VFB = 4.05 -(4.05 + (Ec-Ef)/q) ≈ -0.7V

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