vSync Circuits Tool & IP based synchronization solutions Dr. - - PowerPoint PPT Presentation

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vSync Circuits Tool & IP based synchronization solutions Dr. - - PowerPoint PPT Presentation

Dec 30, 2022 242 likes •425 views

Xilinx Alliance Member vSync Circuits Tool & IP based synchronization solutions Dr. Reuven Dobkin, CTO www.vsyncc.com vSync Circuits EDA & IP company 30-year academic and industrial research experience Company mission:

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Xilinx Alliance Member

www.vsyncc.com

vSync Circuits

Tool & IP based synchronization solutions

  • Dr. Reuven Dobkin, CTO
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Stockholm, 2019

Xilinx Alliance Member

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vSync Circuits

  • EDA & IP company
  • 30-year academic and industrial research experience
  • Company mission:
  • Tool-based Multiple Clock Domain SoC design integration solutions
  • Tool-based Multiple Clock Domain SoC design verification solutions
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Stockholm, 2019

Xilinx Alliance Member

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vSync Circuits products

  • Vincent platform: a complete CDC solution for Multiple

Clock Domain ASIC & FPGA designs

  • + an optional DO-254 package
  • vLinter: a full-scale linter with an effective rule policy

management

  • + an optional DO-254 package
  • vAXIom platform: automatic generation of a customized

AXI-based FPGA design and its verification environment

  • SW/HW integration speed-up through on-board environment generation
  • System verification speed-up through verification environment generation
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Stockholm, 2019

Xilinx Alliance Member

Challenge: Inter-Clock Domain Communication

  • Data transfer between different clock domains should

be performed carefully

  • Incoming data change near receiver clock edge causes

metastability, which may lead to a functional failure due to:

  • Non-deterministic propagation delay
  • Non-deterministic value after metastability resolution

Transmitter Receiver

DATA

CLK_TX CLK_RX

CLK_RX DATA

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Stockholm, 2019

Xilinx Alliance Member

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Asynchronous Failures

Clock tpd tsu+ th In 1 Out 1 In 2 Out 2 Data conflict Long Delay In 3 Out 3 Metastability Terrible data conflict

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SLIDE 6

Stockholm, 2019

Xilinx Alliance Member

Handling non-determinism

  • Non-deterministic delay
  • Settling time → MTBF
  • Non-deterministic value
  • Event-driven logic → special RTL design

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Stockholm, 2019

Xilinx Alliance Member

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Summary

  • Number of Clock Domain Crossings (CDC) is growing
  • More automation is required!
  • Vincent Platform provides:
  • Tool-based multi-clock design integration
  • Correct by design flexible synchronizers
  • Customized for a targeted FPGA/ASIC
  • Auto-constrained for Synthesis and P&R
  • Tool-based CDC verification
  • Static & Dynamic
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Xilinx Alliance Member

Vincent Platform

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Stockholm, 2019

Xilinx Alliance Member

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Vincent platform: vSync Design and Verification Methodology

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Stockholm, 2019

Xilinx Alliance Member

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vGenerator: Summary

vSync Integration

vReset vClkGate vClkSwtch

CLK1 CLK2 TEST_CLK TEST-EN ARST CLKN

ClockDomain-B ClockDomain-C ClockDomain-D

Zynq PS/uBlaze/ Altera SoC/Nios-II/ ARM

ClockDomain-A ClockDomain-E ClockDomain-F ClockDomain-G

LOCKs from DLLs LOCKs CLK-A CLK-B CLK-G ResetA ResetB ResetG ENs ENs

vPTP vPTP vMarker vMarker vNoC vAXI

AXI4 Inter- Connect/ QSyS X

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SLIDE 11

Stockholm, 2019

Xilinx Alliance Member

Vendor Black-box verification

  • vChecker performs Vendor IP auto-recognition and verification
  • Xilinx, Intel/Altera, Synopsys, etc.
  • Verify correct connections to the IP ports
  • User can define a custom black-box (e.g. PCIe bought from third-party)
  • The custom definitions can be ported from another project

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Vendor Black Box

CLK Source1 WR-Clk RD-Clk WR-P1 WR-P2 WR-PN RD-P1 RD-P2 RD-PN

A

CLK_A

B

CLK_B CLK Source2 User logic User logic

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Stockholm, 2019

Xilinx Alliance Member

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RTL simulation with vSync RTL library (1)

  • Default set-up (vsync_rtl_setup.ini is in its default form or no ini-file at all):

# vSync INI File ## # 1. m/s triggering (0 -- for each transaction) vsync_tran_mode # 2. vsync_rand_op_mode: operation mode (0 -- deterministic delay) vsync_rand_op_mode # 3. Delta time around the clock in which m/s can happen, specified in ps. vsync_ms_delta 50

Delay = 70.98 ns

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Stockholm, 2019

Xilinx Alliance Member

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RTL simulation with vSync RTL library (2)

  • Running with non-deterministic delay

# VSync INI File ## # 1. m/s triggering (0 -- for each transaction) vsync_tran_mode # 2. vsync_rand_op_mode: operation mode (2 – random synchronization delay) vsync_rand_op_mode 2 # 3. Delta time around the clock in which m/s can happen, specified in ps. vsync_ms_delta 50

Delay = 101.26 ns

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Stockholm, 2019

Xilinx Alliance Member

Complete CDC solution makes money…

Man power savings: Design, Verification, Synthesis, P&R, Testing Time to market savings

Reliability enhancement

¤ Assuring reliability for released products

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Xilinx Alliance Member

www.vsyncc.com

vLinter

vSync Front-End Linter

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Stockholm, 2019

Xilinx Alliance Member

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vLinter - Goals

  • Identify and report RTL–level problems
  • Multiple rule sets
  • Same data base as vChecker
  • One-time setup
  • An automatic setup using main FPGA vendor project files

(QSF, XPR)

  • Rule policy management
  • Certification process support, e.g.:
  • DO-254
  • Safety Logic
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Stockholm, 2019

Xilinx Alliance Member

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www.vsyncc.com

Thank you!

Contact Information: Reuven Dobkin, info@vsyncc.com