vSync Circuits Tool & IP based synchronization solutions Dr. - PowerPoint PPT Presentation

Xilinx Alliance Member vSync Circuits Tool & IP based synchronization solutions Dr. Reuven Dobkin, CTO www.vsyncc.com

vSync Circuits • EDA & IP company • 30-year academic and industrial research experience • Company mission: • Tool-based Multiple Clock Domain SoC design integration solutions • Tool-based Multiple Clock Domain SoC design verification solutions 2 Stockholm, 2019 Xilinx Alliance Member

vSync Circuits products • Vincent platform: a complete CDC solution for Multiple Clock Domain ASIC & FPGA designs • + an optional DO-254 package • vLinter: a full-scale linter with an effective rule policy management • + an optional DO-254 package • vAXIom platform: automatic generation of a customized AXI-based FPGA design and its verification environment • SW/HW integration speed-up through on-board environment generation • System verification speed-up through verification environment generation 3 Stockholm, 2019 Xilinx Alliance Member

Challenge: Inter-Clock Domain Communication • Data transfer between different clock domains should be performed carefully • Incoming data change near receiver clock edge causes metastability , which may lead to a functional failure due to: • Non-deterministic propagation delay • Non-deterministic value after metastability resolution CLK_RX Transmitter Receiver DATA DATA CLK_TX CLK_RX 4 Stockholm, 2019 Xilinx Alliance Member

Asynchronous Failures Clock t pd In 1 Out 1 Data conflict Long Delay In 2 Out 2 Terrible data conflict In 3 Out 3 t su + t h Metastability 5 Stockholm, 2019 Xilinx Alliance Member

Handling non-determinism • Non-deterministic delay • Settling time → MTBF • Non-deterministic value • Event-driven logic → special RTL design 6 Stockholm, 2019 Xilinx Alliance Member

Summary • Number of Clock Domain Crossings (CDC) is growing • More automation is required! • Vincent Platform provides: • Tool-based multi-clock design integration • Correct by design flexible synchronizers • Customized for a targeted FPGA/ASIC • Auto-constrained for Synthesis and P&R • Tool-based CDC verification • Static & Dynamic 7 Stockholm, 2019 Xilinx Alliance Member

Xilinx Alliance Member Vincent Platform

Vincent platform: vSync Design and Verification Methodology 9 Stockholm, 2019 Xilinx Alliance Member

vGenerator: Summary vSync Integration TEST-EN TEST_CLK CLK-A vClkSwtch ENs LOCKs CLK1 CLK2 CLK-B vClkGate ClockDomain-E ClockDomain-B CLK-G CLKN ENs LOCKs from DLLs vPTP vMarker ResetA ARST ResetB vReset ResetG vNoC ClockDomain-F ClockDomain-C AXI4 Zynq PS/uBlaze/ vPTP vAXI vMarker Inter- Altera SoC/Nios-II/ Connect/ ARM QSyS ClockDomain-D ClockDomain-G ClockDomain-A X 10 Stockholm, 2019 Xilinx Alliance Member

Vendor Black-box verification • vChecker performs Vendor IP auto-recognition and verification • Xilinx, Intel/Altera, Synopsys, etc. • Verify correct connections to the IP ports • User can define a custom black-box (e.g. PCIe bought from third-party) • The custom definitions can be ported from another project CLK CLK Source1 Source2 User logic WR-Clk RD-Clk User logic B WR-P1 RD-P1 Vendor Black Box A WR-P2 RD-P2 CLK_B WR-PN RD-PN CLK_A 11 Stockholm, 2019 Xilinx Alliance Member

RTL simulation with vSync RTL library (1) • Default set-up (vsync_rtl_setup.ini is in its default form or no ini-file at all): # vSync INI File ## # 1. m/s triggering (0 -- for each transaction) Delay = 70.98 ns vsync_tran_mode 0 # 2. vsync_rand_op_mode: operation mode (0 -- deterministic delay) vsync_rand_op_mode 0 # 3. Delta time around the clock in which m/s can happen, specified in ps. vsync_ms_delta 50 12 Stockholm, 2019 Xilinx Alliance Member

RTL simulation with vSync RTL library (2) • Running with non-deterministic delay # VSync INI File ## # 1. m/s triggering (0 -- for each transaction) Delay = 101.26 ns vsync_tran_mode 0 # 2. vsync_rand_op_mode: operation mode (2 – random synchronization delay) vsync_rand_op_mode 2 # 3. Delta time around the clock in which m/s can happen, specified in ps. vsync_ms_delta 50 13 Stockholm, 2019 Xilinx Alliance Member

Complete CDC solution makes money … Man power savings: Design, Verification, Synthesis, P&R, Testing Time to market savings Reliability enhancement ¤ Assuring reliability for released products 14 Stockholm, 2019 Xilinx Alliance Member

Xilinx Alliance Member vLinter vSync Front-End Linter www.vsyncc.com

vLinter - Goals • Identify and report RTL – level problems • Multiple rule sets • Same data base as vChecker • One-time setup • An automatic setup using main FPGA vendor project files (QSF, XPR) • Rule policy management • Certification process support, e.g.: • DO-254 • Safety Logic 16 Stockholm, 2019 Xilinx Alliance Member

www.vsyncc.com Thank you! Contact Information: Reuven Dobkin, info@vsyncc.com 17 Stockholm, 2019 Xilinx Alliance Member