vertically integrated CMOS technology for vertexing applications L. - - PowerPoint PPT Presentation

Monolithic and hybrid pixel sensors in vertically integrated CMOS technology for vertexing applications

• L. Ratti

Università degli Studi di Pavia and INFN Pavia

OUTLINE

Design of 3D monolithic and hybrid pixels for the SuperB Factory

University of Bergamo and INFN Pavia Luigi Gaioni, Massimo Manghisoni, Valerio Re, Gianluca Traversi University of Pavia and INFN Pavia Alessia Manazza, Stefano Zucca

First test results from 3D DNW MAPS characterization

• 3D technology
• design features
• characterization results

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

Experiments at the future particle colliders (or upgrade of present colliders) will set severe requirements for silicon vertex trackers

large hit rate large background power dissipation low mass cooling data sparsification mixed-signal chips digital-to-analog interference small pixel pitch

vertical integration technologies low material budget high granularity small distance from the interaction point

Vertex detectors in future HEP experiments

small amount of support material and interconnection high functional density in DNW MAPS, efficiency loss due to N-wells

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

~ 2.5 cm ~ 3.2 cm

The 3D-IC collaboration

Several groups from US and Europe have been involved in the first 3D MPW for HEP (pixel and strip readout chips for ATLAS, CMS, B-factory, ILC) and photon science applications (X-ray imaging) Single set of masks used for both tiers to save money

identical wafers produced by Chartered (now Globalfoundries) and face-to-face bonded by Tezzaron backside metallization by Tezzaron

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

Tezzaron vertical integration (3D) technology

WB/BB pad

1st wafer

TSV

Inter-tier bond pads

In wafer-level, three-dimensional processes, multiple strata of planar devices are stacked and interconnected using through silicon vias (TSV)

Fabrication of electrically isolated connections through the silicon substrate (TSV formation) Substrate thinning (below 50 um)

3D processes rely upon the following enabling technologies

Inter-layer alignment and mechanical/electrical bonding

Tezzaron Semiconductor technology (via middle approach, vias are made between CMOS and BEOL) can be used to vertically integrate two 130 nm CMOS layers specifically processed by Globalfoundries Fabrication took quite a long time due to a number accidents both at the foundry and at the vertical integration facilities – the first 3D wafers became available by beginning of last summer

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

From 2D to 3D DNW MAPS

A large DNW is used to collect the charge released in the substrate A classical readout channel for capacitive detectors is used for Q-V conversion  gain decoupled from electrode capacitance NMOS devices of the analog section are built in the deep N-well Full CMOS for high performance analog and digital blocks  charge collection inefficiency depending on the relative weight of NW with respect to DNW

What can be gained from going 3D

less PMOS in the sensor layer  improved collection efficiency more room for both analog and digital power and signal routing

Deep N-well monolithic pixels

Tier 1: collecting electrode and NMOS parts of the analog front-end (and a few PMOS) Tier 2: discriminator PMOS parts, digital front-end and peripheral digital readout electronics sensor and analog front-end can be integrated in a different layer from the digital blocks

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

3D DNW MAPS for the ILC vertex tracker

337 ns x2820 0.2 s

bunch train interval intertrain interval Digital readout

0.95 ms

Sparsification based on a token passing scheme Bunch structure of the ILC beam Double hit storage and double 5-bit time stamp register Chip operation tailored on the ILC beam structure

• detection phase, corresponding to the bunch train

interval

• readout phase, corresponding to the intertrain

interval 20 um pitch monolithic pixel

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

1st wafer metal + oxide +2nd wafer substrate

DNW MAPS test structures

Small test structures

single pixels with and w/o detector emulating capacitor shunting the readout channel input (analog only) 3x3 DNW MAPS matrices (analog only, for charge collection tests) 8x8 and 16x16 DNW MAPS matrices (analog and digital, for readout architecture test) ~ 6.3 mm ~ 5.2 mm

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

Analog front-end characterization

Test of single channels and small matrices

DUT is located in the thick tier – signals and power supply are fed through TSVs and inter-tier bond pads

Peaking time of about 1 us, increasing with increasing input charge (as anticipated by simulations due to the non-linearity in the feedback network) Slew rate limitations on the rising edge in a number

• f samples

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

Analog front-end characterization

ENC: 35 - 40 electrons (good agreement with simulations) Estimated DNW capacitance: ~250 fF (about 25% larger than in circuit simulation) Charge sensitivity: ~700 mV/fC (~12% less than the design value) Input dynamic range: ~2000 electrons (good agreement with simulations)

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

DNW sensor test

Obtained by retro- illumination with an infrared laser Collected charge as a function of the laser beam position

Some problems in getting more quantitative data on collection efficiency and charge sharing – laser beam is likely to be scattered from the irregular back-surface of the dice (which was not back-lapped)

Response to a laser pulse

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

Digital readout

Signals from an 8x8 matrix (detail of the first readout cells, fCK=20 MHz) READOUT-CK (clocks the serializer at the chip periphery) CELL-CK (one CELL-CK period is needed to read out a hit from one cell) TOKEN-IN (readout can start after the rising edge) DATA-OUT (address and time-stamp, hit pixels read

• ut serially)

Operation up to 50 MHz seems feasible

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

Digital readout

Npixel x Nbit x Tck = = 64 x 24 x 50 ns = 76.8 us

Signals from an 8x8 matrix (complete readout cycle, fCK=20 MHz) TOKEN-OUT (readout stops

• n the rising edge)

TOKEN-IN DATA-OUT

During the test, all the pixel cells were always found to report a single hit (unless the MASTER-RESET signal is kept active during readout or the kill mask is used)

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

Layer misalignment

always set to 1 never set to 1 always set to 1 (unless killed

• r reset)

level triggered edge triggered Redundant inter-tier connection makes the signal path to and from the wire bond pads more robust

wire bond pad wire bond pad

Single inter-tier connections between circuits on the two tiers – while the single sections work, misalignment by a single inter-tier pad makes the overall circuit non

• perable

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

3D hybrid pixel detectors Design of the SVT layer0 at SuperB has to comply with severe requirements

large background, ~150 MHz/cm2 (including a x5 safety factor), small thickness, <1% X0 vertically integrated, mixed-signal circuit for a pixel detector in high resistivity silicon - fine pitch (50 μm) bump bonding (IZM, Munich) or more advanced technologies (direct bonding by Ziptronix, or u-bump bonding by T-Micro) – based on a 130 nm dual tier CMOS process - 128x32 element chip to be submitted in the next run

3D DNW MAPS sensors

deep N-well sensors were proposed to enable fast readout through pixel-level sparsification and time stamping - DNW sensor in an undepleted substrate, analog front-end for capacitive detectors, analog and digital blocks integrated in separate layers – based on a 130 nm dual tier CMOS process - a 128x96 pixel chip is being designed for the next run

3D options for the SuperB SVT Layer0

Direct bonding (Ziptronix) or u-bump bonding (T-Micro)

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

3D front-end for hybrid pixels: the SuperPix1 chip

Peaking time: 250 ns (slightly dependent on input charge) ENC=190 e- rms @CD=150 fF Charge sensitivity: 50 mV/fC Threshold dispersion: 560/65 e- rms (before/after correction) Power dissipation: 12 uW/pixel Digital section: in-pixel time-stamp, time-ordered triggered or data-push readout

CF C1 C2 VGTHR

THR DAC shift-in shift-out polarity select A(s) TIER 1 TIER 2

50 um pitch Polarity selection

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

Analog front-end for the ApselVI 3D MAPS chip

Peaking time: 320 ns ENC=38 e- rms @CD=290 fF Charge sensitivity: 875 mV/fC Power dissipation: 33 uW/pixel Threshold dispersion: 95/12 e- rms (before/after correction) Blocks for voltage drop (along power and ground lines) and temperature compensation Digital section: same as for the hybrid pixel front-end RC-CR shaping 50 um pitch

CF C1 C2 VREF A(s)

VGTHR

THR DAC shift-in shift-out TIER 1 TIER 2

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

Conclusion

First tests on 3D deep N-well MAPS prototypes for vertexing applications have been performed Planar wafers from the same run are being vertically integrated – new chips by beginning 2012

analog section works fine – some linearity issues (slew rate limitations), thorough characterization of the charge collection properties still missing (tests with radioactive sources are needed)

• nly part of the functionalities of the digital

(single hit readout, reset, kill mask) section could be tested – no inter-tier interconnection between circuits likely due to misalignment analog section could be tested as a result of redundancy in inter-tier interconnection under wire bond pads – also TSVs do their job

The design of new 3D DNW MAPS and of a 3D front-end chip for hybrid pixels is in progress – submission by end of March 2012

Backup slides

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

gX TS tko gY tki gX TS tko gY tki gX TS tko gY tki gX TS tko gY tki gX TS tko gY tki gX TS tko gY tki gX TS tko gY tki gX TS tko gY tki gX TS tko gY tki gX TS tko gY tki gX TS tko gY tki gX TS tko gY tki gX TS tko gY tki gX TS tko gY tki Y=1 Y=2 Y=240 X=256 X=2 X=1 gX TS tko gY tki gX TS tko gY tki gX TS tko gY tki gX TS tko gY tki

Token passing readout architecture (240x256 DNW MAPS matrix)

MUX

FirstTokenIn LastTokenOut DataOut TSBUF TSBUF TSBUF ReadOutCLK

Time stamp counter gX=GetX gY=GetY TS=TimeStampOut tki=TokenIn tko=TokenOut 8 8 5

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

Digital readout at 50 MHz

Signals from an 8x8 matrix (detail of the first readout cells) READOUT-CK (clocks the serializer at the chip periphery) CELL-CK (one CELL-CK period is needed to read out a hit from one cell) TOKEN-IN (readout starts

• n the rising edge)

DATA-OUT (address and time-stamp, hit pixels read

• ut serially)

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

Digital readout at 50 MHz

Signals from an 8x8 matrix (complete readout cycle) Npixel x Nbit x Tck = = 64 x 24 x 20 ns = 30.7 us TOKEN-OUT (readout stops

• n the rising edge)

TOKEN-IN DATA-OUT

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

Channel response

Slight nonlinearity due to the nonlinear shaper feedback network

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

TS Co mp .

DATA-OUT HIT-OR-OUT

by F. Morsani, Pisa

Time ordered readout with in-pixel time stamp

No macropixel

A readout TS enters the pixel and a HIT-OR-OUT is generated for columns with hits associated to that TS A column is read only if HIT- OR-OUT=1

Timestamp (TS) is broadcast to pixels; pixel latches the current TS when fired Matrix readout is timestamp-ordered

DATA-OUT (1 bit) is generated for pixels in the active column with hits associated to that TS More in pixel logic with 3D integration Readout can be data push and

• r triggered

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

AVDDperipheral AVDDpixel AGNDpixel AGNDperipheral

• M. Manghisoni, E. Quartieri et al.,“High Accuracy Injection Circuit for Pixel-Level Calibration of Readout Electronics”, presented at the 2010

IEEE Nuclear Science Symposium Conference, Knoxville, USA, October 30 - November 6 2010.

I=120 nA Isib≈120 nA Itransc ≈ 2.5 nA

Voltage drop compensation

• L. Ratti, “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8th Hiroshima Symposium, 5-8 December 2011

Effects on output waveform

w/o voltage drop compensation with voltage drop compensation AVDD=1.5 V-ΔVd, AGND=ΔVd Voltage drop is simulated as a symmetrical voltage variation in the analog power (AVDD) and ground (AGND) lines