[PPT] - Testbench - -- interface entity reg32 is port (CLK, rst_n, load : in PowerPoint Presentation

SLIDE 1

Testbench - Example: Register

Calcolatori Elettronici e Sistemi Operativi

32-bit register

library ieee; use ieee.std_logic_1164.all;

- interface

entity reg32 is port (CLK, rst_n, load : in std_logic; D : in std_logic_vector(31 downto 0); Q : out std_logic_vector(31 downto 0)); end reg32; architecture behav of reg32 is begin process (CLK, rst_n) begin if (rst_n = '0') then Q <= (others => '0'); elsif rising_edge(CLK) and load='1' then Q <= D after 1 ns; end if; end process; end behav;

file: reg.vhdl

Testbench

Testbench Device Under Test

RESET CLK INPUTS OUTPUTS

Inputs Generator

Reset Generator Clock Generator

Testbench

Testbench Device Under Test

RESET CLK INPUTS OUTPUTS

Read file Data File

Reset Generator Clock Generator

SLIDE 2

Testbench for 32-bit register: Data File

file: data.txt

10111001010101111101000100001011 1 01101011101001101100110000001110 1 01111001110110100110010111110101 1 10011011010100000100100011110100 11010011110111101011110010101000 00111100100110011100111110100101 1 ... ...

Testbench for 32-bit register

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use STD.textio.all;

- interface

entity TB is end TB;

- architecture

architecture behav of TB is constant CLK_SEMIPERIOD0: time := 25 ns; constant CLK_SEMIPERIOD1: time := 15 ns; constant CLK_PERIOD : time := CLK_SEMIPERIOD0+CLK_SEMIPERIOD1; constant RESET_TIME : time := 3*CLK_PERIOD + 9 ns;

file: TB.vhdl

Testbench for 32-bit register

signal CLK, rst_n : std_logic;

- signals for debugging and tb control

signal count : std_logic_vector(23 downto 0) := (others=> '0'); signal int_count : integer := 0; signal start : integer := 0; signal done : integer := 0; signal counter_data : std_logic_vector(23 downto 0) := (others=> '0'); signal int_counter_data : integer := 0;

- signals for DUT (Device Under Test)

signal load : std_logic := '0'; signal D : std_logic_vector(31 downto 0); signal Q : std_logic_vector(31 downto 0);

file: TB.vhdl

Testbench for 32-bit register

- DUT declaration

component reg32 is port ( CLK, rst_n, load : in std_logic; D : in std_logic_vector(31 downto 0); Q : out std_logic_vector(31 downto 0) ); end component;

- TB architecture definition

begin

- DUT instance

DUT : reg32 port map ( CLK => CLK, rst_n => rst_n, load => load, D => D, Q => Q );

file: TB.vhdl

SLIDE 3

Testbench for 32-bit register

- RESET

start_process: process begin rst_n <= '1'; wait for 1 ns; rst_n <= '0'; wait for RESET_TIME; rst_n <= '1'; start <= 1; wait; end process start_process;

file: TB.vhdl

1 ns RESET_TIME

used to start reading from datafile

Testbench for 32-bit register

- read from datafile

read_file_process: process(clk) file infile : TEXT open READ_MODE is "data.txt"; variable inputline : LINE; variable in_D : bit_vector(D'range); variable in_load : bit; begin if (clk='0') and (start = 1) then

- read new data from file

if not endfile(infile) then readline(infile, inputline); read(inputline, in_D); D <= to_UX01(in_D); readline(infile, inputline); read(inputline, in_load); load <= to_UX01(in_load); readline(infile, inputline); -- separator (empty line) counter_data <= std_logic_vector(unsigned(counter_data) + 1); int_counter_data <= int_counter_data + 1; else done <= 1; end if; end if; end process read_file_process;

file: TB.vhdl

used to keep track of data read D input for DUT load input for DUT data updated on the falling edge

Testbench for 32-bit register (v1)

- terminate the simulation when there are no more data in datafile

done_process: process(done) variable outputline : LINE; begin if (done=1) then write(outputline, string'("End simulation - ")); write(outputline, string'("cycle counter is ")); write(outputline, int_count); writeline(output, outputline); assert false report "NONE. End of simulation." severity failure; end if; end process done_process; end behav;

file: TB.vhdl

Testbench for 32-bit register (v1)

- CLOCK generator

clk_process: process begin if CLK = '0' then CLK <= '1'; wait for CLK_SEMIPERIOD1; else CLK <= '0'; wait for CLK_SEMIPERIOD0; count <= std_logic_vector(unsigned(count) + 1); int_count <= int_count + 1; end if; end process clk_process;

file: TB.vhdl

CLK_SEMIPERIOD0 CLK_SEMIPERIOD1

used to keep track of clock cycles

SLIDE 4

Testbench for 32-bit register (v2)

- CLOCK generator

clk_process: process begin if CLK = '0' then CLK <= '1'; wait for CLK_SEMIPERIOD1; else CLK <= '0'; wait for CLK_SEMIPERIOD0; count <= std_logic_vector(unsigned(count) + 1); int_count <= int_count + 1; end if; if done = 1 then wait; end if; end process clk_process;

file: TB.vhdl

No more events will be generated (simulation terminates)

32-bit register: simulation results (v1)

End simulation - cycle counter is 22 TB.vhdl:110:13:(assertion failure): NONE. End of simulation. ./tb:error: assertion failed End simulation - cycle counter is 22 TB.vhdl:110:13:(assertion failure): NONE. End of simulation. ./tb:error: assertion failed

simulation output Waveforms

Exercises

Implement and simulate (using a testbench): Combinatorial logic

Multiplexer, shifter, adder

Double sequence recognizer

Detect seq1=1011011 and seq2=10101

Exercise: Ones counter

Calcolatori Elettronici e Sistemi Operativi

SLIDE 5

Ones counter

nescounter

8 8

X DATAIN CALC OUTP READY OK

OUTP: total number of bits equal to '1' received on X DATAIN=1 signals a new input data CALC=1 signals that input data are finished: provide result READY=1 the device is ready to receive a new data OK=1 the device finished the computation

the result on OUTP is ready and valid a new computation can start

Ones counter

ASM chart ctrlunit datapath toplevel testbench

READY A <= X

WAITDATA

CALC DATAIN 1 1 ONES <= ONES+1 A <= A>>1

INC

A <= A>>1

SHIFT

READY OK A <= X

INIT

DATAIN 1 ONES <= 0 A <= A>>1

START

1 CALC 1 A <= A>>1

CALC_A

A=0 1 1 A=0 LSB_A 1 1 LSB_A 1

INC SHIFT

A(0) A(0) A(0) A(0)

A

loadA selA

X rsl ONES

loadONES selONES

+ 1 =0

OUTP

zA

LSB_A

8 8 8 8 8 8

Ones counter

ctrlunit

interface

clk, reset, control signals from extern scan the asm chart to find status signals

FSM evolution ()

use also “when others”

find control signals for datapath ()

write outputs expression

do not forget any “else”

complete the interface

SLIDE 6

Ones counter: ctrlunit

library ieee; use ieee.std_logic_1164.all;

- interface

entity ctrlunit is port ( CLK, rst_n : in std_logic;

- control inputs

DATAIN : in std_logic; CALC : in std_logic;

- control outputs

READY : out std_logic; OK : out std_logic; loadA : out std_logic; selA : out std_logic; loadONES : out std_logic; selONES : out std_logic;

- status signals

LSB_A : in std_logic; zA : in std_logic ); end ctrlunit;

file: ctrlunit.vhdl

Ones counter: ctrlunit

architecture behav of ctrlunit is type statetype is (INIT, START, INC, SHIFT, CALC_A, WAITDATA); signal state, nextstate : statetype; begin

- FSM

state <= INIT when rst_n='0' else nextstate when rising_edge(CLK); process (state, DATAIN, CALC, LSB_A, zA) begin case state is when INIT => if CALC /= '0' then nextstate <= INIT; elsif DATAIN /= '1' then nextstate <= INIT; else nextstate <= START; end if;

file: ctrlunit.vhdl

Ones counter: ctrlunit

when START => if LSB_A = '0' then nextstate <= SHIFT; else nextstate <= INC; end if; when INC => if zA = '1' then nextstate <= WAITDATA; elsif LSB_A = '1' then nextstate <= INC; else nextstate <= SHIFT; end if; when SHIFT => if zA = '1' then nextstate <= WAITDATA; elsif LSB_A = '1' then nextstate <= INC; else nextstate <= SHIFT; end if;

file: ctrlunit.vhdl

Ones counter: ctrlunit

when CALC_A => if LSB_A = '0' then nextstate <= SHIFT; else nextstate <= INC; end if; when WAITDATA => if CALC = '1' then nextstate <= INIT; elsif DATAIN = '0' then nextstate <= WAITDATA; else nextstate <= CALC_A; end if; when others => nextstate <= INIT; end case; end process;

file: ctrlunit.vhdl

SLIDE 7

Ones counter: ctrlunit

- OUTPUTS

loadA <= '1' when state=INIT or state=START or state=INC or state=SHIFT or state=WAITDATA or state=CALC_A else '0'; selA <= '1' when state=START or state=SHIFT or state=INC or state=CALC_A else '0'; loadONES <= '1' when state=START or state=INC else '0'; selONES <= '1' when state=INC else '0'; READY <= '1' when state=INIT or state=WAITDATA else '0'; OK <= '1' when state=INIT else '0'; end behav;

file: ctrlunit.vhdl

Ones counter

datapath

interface

clk, reset, data outputs from specifications control signals from control unit status signals for control unit

registers mux that feed registers

do not forget any “when” or “else”

combinatorial components status signals

do not forget any “else”

data outputs

Ones counter: datapath

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

- interface

entity datapath is port ( CLK, rst_n : in std_logic;

- data inputs

X : in std_logic_vector(7 downto 0);

- data outputs

OUTP : out std_logic_vector(7 downto 0);

- control signals

loadA : in std_logic; selA : in std_logic; loadONES : in std_logic; selONES : in std_logic;

- status signals

LSB_A : out std_logic; zA : out std_logic ); end datapath;

file: datapath.vhdl

Ones counter: datapath

architecture s of datapath is signal A, A_in : std_logic_vector(7 downto 0); signal ONES, ONES_in : std_logic_vector(7 downto 0); signal adder1 : std_logic_vector(ONES'range); begin

- REGISTERS

A <= (others=>'0') when rst_n='0' else A_in when rising_edge(CLK) and loadA='1'; ONES <= (others=>'0') when rst_n='0' else ONES_in when CLK'event and CLK='1' and loadONES='1';

- MUX for A

with selA select A_in <= X when '0' , '0' & A(7 downto 1) when others;

- MUX for ONES

ONES_in <= (others => '0') when selONES='0' else adder1;

file: datapath.vhdl

SLIDE 8

Ones counter: datapath

- ADDER

adder1 <= std_logic_vector( unsigned(ONES) + 1 );

- status signals

LSB_A <= A(0); zA <= '1' when unsigned(A) = 0 else '0';

- data outputs

OUTP <= ONES; end s;

file: datapath.vhdl

Ones counter: datapath (struct)

library ieee; use ieee.std_logic_1164.all; entity reg8 is port ( CLK, rst_n : in std_logic; load : in std_logic; D : in std_logic_vector(7 downto 0); Q : out std_logic_vector(7 downto 0) ); end reg8; architecture s of reg8 is begin Q <= (others=>'0') when rst_n='0' else D when rising_edge(CLK) and load='1'; end s;

file: reg8.vhdl

Ones counter: datapath (struct)

library ieee; use ieee.std_logic_1164.all; entity mux2x8 is port ( sel : in std_logic; I0 : in std_logic_vector(7 downto 0); I1 : in std_logic_vector(7 downto 0); Y : out std_logic_vector(7 downto 0) ); end mux2x8; architecture s of mux2x8 is begin with sel select Y <= I0 when '0' , I1 when others; end s;

file: mux2x8.vhdl

Ones counter: datapath (struct)

library ieee; use ieee.std_logic_1164.all; entity rshift is port ( I : in std_logic_vector(7 downto 0); Y : out std_logic_vector(7 downto 0) ); end rshift; architecture s of rshift is begin Y <= '0' & I(7 downto 1); end s;

file: rshift.vhdl

SLIDE 9

Ones counter: datapath (struct)

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity adder is port ( A : in std_logic_vector(7 downto 0); B : in std_logic_vector(7 downto 0); Y : out std_logic_vector(7 downto 0) ); end adder; architecture s of adder is begin Y <= std_logic_vector( unsigned(A) + unsigned(B) ); end s;

file: adder.vhdl

Ones counter: datapath (struct)

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity zerodetect is port ( A : in std_logic_vector(7 downto 0); Y : out std_logic ); end zerodetect; architecture s of zerodetect is begin Y <= '1' when unsigned(A) = 0 else '0'; end s;

file: zerodetect.vhdl

Ones counter: datapath (struct)

library ieee; use ieee.std_logic_1164.all;

- interface

entity datapath is port ( CLK, rst_n : in std_logic;

- data inputs

X : in std_logic_vector(7 downto 0);

- data outputs

OUTP : out std_logic_vector(7 downto 0);

- control signals

loadA : in std_logic; selA : in std_logic; loadONES : in std_logic; selONES : in std_logic;

- status signals

LSB_A : out std_logic; zA : out std_logic ); end datapath;

file: datapath.vhdl

Ones counter: datapath (struct)

architecture struct of datapath is component reg8 is port ( CLK, rst_n : in std_logic; load : in std_logic; D : in std_logic_vector(7 downto 0); Q : out std_logic_vector(7 downto 0) ); end component; component mux2x8 is port ( sel : in std_logic; I0 : in std_logic_vector(7 downto 0); I1 : in std_logic_vector(7 downto 0); Y : out std_logic_vector(7 downto 0) ); end component; component rshift is port ( I : in std_logic_vector(7 downto 0); Y : out std_logic_vector(7 downto 0) ); end component;

file: datapath.vhdl

SLIDE 10

Ones counter: datapath (struct)

component adder is port ( A : in std_logic_vector(7 downto 0); B : in std_logic_vector(7 downto 0); Y : out std_logic_vector(7 downto 0) ); end component; component zerodetect is port ( A : in std_logic_vector(7 downto 0); Y : out std_logic ); end component; signal A_out, A_in : std_logic_vector(7 downto 0); signal ONES_out, ONES_in: std_logic_vector(7 downto 0); signal adder1_out : std_logic_vector(7 downto 0); signal shifter_out : std_logic_vector(7 downto 0);

file: datapath.vhdl

Ones counter: datapath (struct)

begin

- REGISTERS

A : reg8 port map (CLK, rst_n, loadA, A_in, A_out); ONES : reg8 port map (CLK, rst_n, loadONES, ONES_in, ONES_out);

- MUX for A

MUX_A: mux2x8 port map (selA, X, shifter_out, A_in);

- MUX for ONES

MUX_ONES: mux2x8 port map ( selONES, (others => '0'), adder1_out, ONES_in ); SHIFTER : rshift port map (A_out, shifter_out);

- ADDER

ADDER1 : adder port map (ONES_out, "00000001", adder1_out);

- status signals

LSB_A <= A_out(0); ZD : zerodetect port map(A_out, zA);

- data outputs

OUTP <= ONES_out; end struct;

file: datapath.vhdl

Ones counter

toplevel

interface control unit and datapath declarations instantiate control unit and datapath add signals to connect CTRL-DP

Ones counter: top level

library ieee; use ieee.std_logic_1164.all;

- interface

entity onescounter is port ( CLK, rst_n : in std_logic;

- data inputs

X : in std_logic_vector(7 downto 0);

- data outputs

OUTP : out std_logic_vector(7 downto 0);

- control inputs

DATAIN : in std_logic; CALC : in std_logic;

- control outputs

READY : out std_logic; OK : out std_logic ); end onescounter;

file: onescounter.vhdl

SLIDE 11

Ones counter: top level

architecture struct of onescounter is component ctrlunit is port ( CLK, rst_n : in std_logic; DATAIN : in std_logic; CALC : in std_logic; READY : out std_logic; OK : out std_logic; loadA : out std_logic; selA : out std_logic; loadONES : out std_logic; selONES : out std_logic; LSB_A : in std_logic; zA : in std_logic ); end component;

file: onescounter.vhdl

Ones counter: top level

component datapath is port ( CLK, rst_n : in std_logic; X : in std_logic_vector(7 downto 0); OUTP : out std_logic_vector(7 downto 0); loadA : in std_logic; selA : in std_logic; loadONES : in std_logic; selONES : in std_logic; LSB_A : out std_logic; zA : out std_logic ); end component; signal loadA : std_logic; signal selA : std_logic; signal loadONES : std_logic; signal selONES : std_logic; signal LSB_A : std_logic; signal zA : std_logic;

file: onescounter.vhdl

Ones counter: top level

begin CTRL : ctrlunit port map ( CLK, rst_n, DATAIN => DATAIN, CALC => CALC, READY => READY, OK => OK, loadA => loadA, selA => selA, loadONES => loadONES, selONES => selONES, LSB_A => LSB_A, zA => zA ); DP : datapath port map ( CLK, rst_n, X => X, OUTP => OUTP, loadA => loadA, selA => selA, loadONES => loadONES, selONES => selONES, LSB_A => LSB_A, zA => zA ); end struct;

file: onescounter.vhdl

Ones counter

testbench

constants (TCLK , TRESET) device declaration device instance signals: clock, reset and debug signals signals: device inputs and outputs processes to generate reset and clock processes to generate device inputs

SLIDE 12

Ones counter: testbench

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use STD.textio.all;

- interface

entity TB is end TB; architecture behav of TB is constant CLK_SEMIPERIOD0: time := 25 ns; constant CLK_SEMIPERIOD1: time := 15 ns; constant CLK_PERIOD : time := CLK_SEMIPERIOD0+CLK_SEMIPERIOD1; constant RESET_TIME : time := 3*CLK_PERIOD + 9 ns;

file: TB.vhdl

Ones counter: testbench

signal CLK, rst_n : std_logic; signal count : std_logic_vector(23 downto 0) := (others=> '0'); signal int_count : integer := 0; signal start : integer := 0; signal done : integer := 0; signal counter_data : std_logic_vector(23 downto 0) := (others=> '0'); signal int_counter_data : integer := 0; signal X : std_logic_vector(7 downto 0); signal OUTP : std_logic_vector(7 downto 0); signal DATAIN : std_logic := '0'; signal CALC : std_logic := '1'; signal READY : std_logic; signal OK : std_logic;

file: TB.vhdl

Ones counter: testbench

component onescounter is port ( CLK, rst_n : in std_logic; X : in std_logic_vector(7 downto 0); OUTP : out std_logic_vector(7 downto 0); DATAIN : in std_logic; CALC : in std_logic; READY : out std_logic; OK : out std_logic ); end component;

file: TB.vhdl

Ones counter: testbench

begin DUT : onescounter port map ( CLK => CLK, rst_n => rst_n, X => X, OUTP => OUTP, DATAIN => DATAIN, CALC => CALC, READY => READY, OK => OK ); start_process: process begin rst_n <= '1'; wait for 1 ns; rst_n <= '0'; wait for RESET_TIME; rst_n <= '1'; start <= 1; wait; end process start_process;

file: TB.vhdl

SLIDE 13

Ones counter: testbench

clk_process: process begin if CLK = '0' then CLK <= '1'; wait for CLK_SEMIPERIOD1; else CLK <= '0'; wait for CLK_SEMIPERIOD0; count <= std_logic_vector(unsigned(count) + 1); int_count <= int_count + 1; end if; end process clk_process;

file: TB.vhdl

Ones counter: testbench

read_file_process: process(clk) file infile : TEXT open READ_MODE is "data.txt"; variable inputline : LINE; variable in_X : bit_vector(X'range); variable in_DATAIN : bit; variable in_CALC : bit; begin if (clk='0') and (start = 1) and (READY='1') then

- read new data from file

if not endfile(infile) then readline(infile, inputline); read(inputline, in_X); X <= to_UX01(in_X); readline(infile, inputline); read(inputline, in_DATAIN); DATAIN <= to_UX01(in_DATAIN); readline(infile, inputline); read(inputline, in_CALC); CALC <= to_UX01(in_CALC); readline(infile, inputline); counter_data<= std_logic_vector(unsigned(counter_data)+1); int_counter_data <= int_counter_data + 1; else done <= 1; end if; end if; end process read_file_process;

file: TB.vhdl

Ones counter: testbench

done_process: process(done) variable outputline : LINE; begin if (done=1) then write(outputline, string'("End simulation - ")); write(outputline, string'("cycle counter is ")); write(outputline, int_count); writeline(output, outputline); assert false report "NONE. End of simulation." severity failure; end if; end process done_process; end behav;

file: TB.vhdl

Ones counter: notes

Device must be:

synthesizable

no: wait for, files (allowed in testbench)

efficient

avoid ctrl/datapath mixing (acceptable in testbench) keep control on resource sharing and allocation

SLIDE 14

Timing: critical path

Cycle time is bounded by the “critical path”

slowest path between two registers (even not distinct)

take into account multi-cycle paths and false paths

Tclk ≥ 11 ns

COMB1 COMB2

T = 5 ns T = 8 ns T = 1 ns TCO = 1 ns TSU = 1 ns

Timing: critical path

Cycle time is bounded by the “critical path”

slowest path between two registers (even not distinct)

take into account multi-cycle paths and false paths A <= X Q <= A+Q

S1 S2 S3

A

+

Q

2-cycles path

Timing: critical path

Cycle time is bounded by the “critical path”

slowest path between two registers (even not distinct)

take into account multi-cycle paths and false paths

f3 f2 f1 A B C Y X

If in ctrl-unit there is not any: Y <= f1(f2(f3(A))) the path: Af3MUXf2MUXf1Y is a false path

Timing: clock skew

CLK CLK2 CLK1 TSKEW available time

CLK1 time CLK2

SLIDE 15

Timing: cycle time

CLK time

TRCO TCOMB TSKEW TSLACK TRSU

TCLK ≥ TRCO + TCOMB + TRSU + TSKEW TCLK ≥ TRCO + TCOMB + TRSU + TSKEW TSLACK = TCLK - (TRCO + TCOMB + TRSU + TSKEW)

Timing: device times

From input to output: TCOMB (combinatorial propagation delay) From input to register: TSU (setup time) From register to output: TCO (clock-to-output time) From register to register: TCLK (cycle time)

C O M B C O M B C O M B R e g i s t e r s R e g i s t e r s

Inputs Output1 Output2

TCOMB TSU TCO TCLK

Timing: metastability

I A B C

TRSU TRH

stability window

CLK time I A

metastability exiting from metastability time to resolve metastability stability window B must be stable here

Timing: metastability

CLK time

stability window stability window “Equivalent” metastability window K1

pmeta TCLK

Probability (per second) to enter in metastability

Probability that register is still metastable after

SLIDE 16

Timing: metastability

Maximize MTBF maximize TSLACK

I A B C

Synchronizer A

loadA selA

X rsl ONES

loadONES selONES

+ 1 =0

OUTP

zA

LSB_A

8 8 8 8 8 8

Moore

READY A <= X

WAITDATA

CALC DATAIN 1 1 ONES <= ONES+1 A <= A>>1

INC

A <= A>>1

SHIFT

READY OK A <= X

INIT

DATAIN 1 ONES <= 0 A <= A>>1

START

1 CALC 1 A <= A>>1

CALC_A

A=0 1 1 A=0 LSB_A 1 1 LSB_A 1

INC SHIFT

A(0) A(0) A(0) A(0)

8 8 8 8 8 8

IN

OUT

T1 = TRco + Tsh + Tmux + TRsu T2 = TRco + Tadd + Tmux + TRsu T3 = TRco + T + TRsu

A

loadA selA

X rsl ONES

loadONES selONES

+ 1 =0

OUTP

zA

LSB_A

8 8 8 8 8 8

Moore

READY A <= X

WAITDATA

CALC DATAIN 1 1 ONES <= ONES+1 A <= A>>1

INC

A <= A>>1

SHIFT

READY OK A <= X

INIT

DATAIN 1 ONES <= 0 A <= A>>1

START

1 CALC 1 A <= A>>1

CALC_A

A=0 1 1 A=0 LSB_A 1 1 LSB_A 1

INC SHIFT

A(0) A(0) A(0) A(0)

IN

OUT

T4 = TRco + Tcomp + T + TRsu T5 = TRco + T + TRsu

A

loadA selA

X rsl ONES

loadONES selONES

+ 1 =0

OUTP

zA

LSB_A

8 8 8 8 8 8

Moore

READY A <= X

WAITDATA

CALC DATAIN 1 1 ONES <= ONES+1 A <= A>>1

INC

A <= A>>1

SHIFT

READY OK A <= X

INIT

DATAIN 1 ONES <= 0 A <= A>>1

START

1 CALC 1 A <= A>>1

CALC_A

A=0 1 1 A=0 LSB_A 1 1 LSB_A 1

INC SHIFT

A(0) A(0) A(0) A(0)

8

IN

OUT

T6 = TRco + T + Tmux + TRsu T7 = TRco + T + TRsu

SLIDE 17

A

loadA selA

X rsl ONES

loadONES selONES

+ 1 =0

OUTP

zA

LSB_A

8 8 8 8 8 8

Moore

READY A <= X

WAITDATA

CALC DATAIN 1 1 ONES <= ONES+1 A <= A>>1

INC

A <= A>>1

SHIFT

READY OK A <= X

INIT

DATAIN 1 ONES <= 0 A <= A>>1

START

1 CALC 1 A <= A>>1

CALC_A

A=0 1 1 A=0 LSB_A 1 1 LSB_A 1

INC SHIFT

A(0) A(0) A(0) A(0)

SHIFT

Moore

IN

OUT

T8 = TRco + T + Tmux + TRsu T9 = TRco + T + TRsu Tcrit = MAX(T1, T2, T3, T4, T5, T6, T7, T8. T9)

READY A <= X

WAITDATA

CALC DATAIN 1 1 A <= A>>1

SHIFT

READY OK A <= X

INIT

DATAIN 1 A <= A>>1

START

1 CALC 1 A <= A>>1

CALC_A

A=0 1 1 LSB_A 1

SHIFT

A(0) A(0) A(0) ONES <= 1 ONES <= ONES+1 ONES <= ONES+1 ONES <=0

A

loadA selA

X rsl ONES

loadONES selONES

+ 1 =0

OUTP

zA

LSB_A

8 8 8 8 8 8

1

READY A <= X

WAITDATA

CALC DATAIN 1 1 A <= A>>1

SHIFT

READY OK A <= X

INIT

DATAIN 1 A <= A>>1

START

1 CALC 1 A <= A>>1

CALC_A

A=0 1 1 LSB_A 1

SHIFT

A(0) A(0) A(0) ONES <= 1 ONES <= ONES+1 ONES <= ONES+1 ONES <=0

A

loadA selA

X rsl ONES

loadONES selONES

+ 1 =0

OUTP

zA

LSB_A

8 8 8 8 8 8

1

SHIFT

8

IN

OUT

Ta = TRco + Tcomp + T + TRsu Tb = TRco + T + TRsu

Mealy

READY A <= X

WAITDATA

CALC DATAIN 1 1 A <= A>>1

SHIFT

READY OK A <= X

INIT

DATAIN 1 A <= A>>1

START

1 CALC 1 A <= A>>1

CALC_A

A=0 1 1 LSB_A 1

SHIFT

A(0) A(0) A(0) ONES <= 1 ONES <= ONES+1 ONES <= ONES+1 ONES <=0

A

loadA selA

X rsl ONES

loadONES selONES

+ 1 =0

OUTP

zA

LSB_A

8 8 8 8 8 8

1

A <= A>>1 1

SHIFT

LSB_A

IN

OUT

Ta' = TRco + Tcomp + T + Tmux + TRsu

Mealy

SLIDE 18

READY A <= X

WAITDATA

CALC DATAIN 1 1 A <= A>>1

SHIFT

READY OK A <= X

INIT

DATAIN 1 A <= A>>1

START

1 CALC 1 A <= A>>1

CALC_A

A=0 1 1 LSB_A 1

SHIFT

A(0) A(0) A(0) ONES <= 1 ONES <= ONES+1 ONES <= ONES+1 ONES <=0

A

loadA selA

X rsl ONES

loadONES selONES

+ 1 =0

OUTP

zA

LSB_A

8 8 8 8 8 8

1

SHIFT

Mealy

IN

OUT

Tc = TRco + T + Tmux + TRsu Tcrit = MAX(T1, T2, T3, T4, T5, T6, T7, T8. T9, Ta, Tb, Tc)

S0

D > A+B 1

+ A B > D

DmajAB seladd2

C Mealy

S1

IN

OUT

Ta = TRco + T + Tmux + Tadd + Tcomp + T + TRsu