Datapaths and Control Digital systems perform sequences of - - PowerPoint PPT Presentation

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Digital Design — Chapter 4 — Sequential Basics 1

Datapaths and Control

 Digital systems perform sequences of

• perations on encoded data

 Datapath

 Combinational circuits for operations  Registers for storing intermediate results

 Control section: control sequencing

 Generates control signals

 Selecting operations to perform  Enabling registers at the right times

 Uses status signals from datapath

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Digital Design — Chapter 4 — Sequential Basics 2

Example: Complex Multiplier

 Cartesian form, fixed-point

 operands: 4 integer, 12 fraction bits  result: 8 pre-, 24 post-binary-point bits

 Subject to tight area constraints

i r

ja a a + =

i r

jb b b + = ) ( ) (

r i i r i i r r i r

b a b a j b a b a jp p ab p + + − = + = =

 4 multiplies, 1 add, 1 subtract

 Perform sequentially using 1 multiplier, 1

adder/subtracter

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Digital Design — Chapter 4 — Sequential Basics 3

Complex Multiplier Datapath

1 1

D CE Q clk D CE Q clk

× ±

D CE Q clk D CE Q clk

p_r p_i a_r a_i b_r b_i a_sel b_sel pp1_ce pp2_ce sub p_r_ce p_i_ce clk

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Digital Design — Chapter 4 — Sequential Basics 4

Complex Multiplier in Verilog

m

• dul

ul e m ul t i pl i e r ( out put r e g s i gne d [ 7: - 24] p_r , p_i , i nput s i gne d [ 3: - 12] a _r , a _i , b_r , b_i , i nput c l k, r e s e t , i nput _r dy ) ; r e g a _s e l , b_s e l , pp1_c e , pp2_c e , s ub, p_r _c e , p_i _c e ; wi r e s i gne d e d [ 3: - 12] a _ope r a nd, b_ope r a nd; wi r e s i gne d e d [ 7: - 24] pp, s um r e g s i gne d e d [ 7: - 24] pp1, pp2; . . .

Verilog

Digital Design — Chapter 4 — Sequential Basics 5

Complex Multiplier in Verilog

a s s i g i gn a _ope r a nd = ~a _s e l ? a _r : a _i ; a s s i g i gn b_ope r a nd = ~b_s e l ? b_r : b_i ; a s s i g i gn pp = {{4{a _ope r a nd[ 3] }}, a _ope r a nd, 12' b0} * {{4{b_ope r a nd[ 3] }}, b_ope r a nd, 12' b0}; a l wa y a ys @ ( pos e dge c l k) / / Pa r t i a l pr oduc t 1 r e gi s t e r i f ( pp1_c e ) pp1 <= pp; a l wa y a ys @ ( pos e dge c l k) / / Pa r t i a l pr oduc t 2 r e gi s t e r i f ( pp2_c e ) pp2 <= pp; a s s i g i gn s um = ~s ub ? pp1 + pp2 : pp1 - pp2; a l wa y a ys @ ( pos e dge c l k) / / Pr oduc t r e a l - pa r t r e gi s t e r i f ( p_r _c e ) p_r <= s um ; a l wa y a ys @ ( pos e dge c l k) / / Pr oduc t i m a gi na r y- pa r t r e gi s t e r i f ( p_i _c e ) p_i <= s um ; . . . e ndm

• dul e

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Digital Design — Chapter 4 — Sequential Basics 6

Multiplier Control Sequence

 Avoid resource conflict  First attempt

• 1. a_r * b_r → pp1_reg
• 2. a_i * b_i → pp2_reg
• 3. pp1 – pp2 → p_r_reg
• 4. a_r * b_i → pp1_reg
• 5. a_i * b_r → pp2_reg
• 6. pp1 + pp2 → p_i_reg

 Takes 6 clock cycles

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Digital Design — Chapter 4 — Sequential Basics 7

Multiplier Control Sequence

 Merge steps where no resource conflict  Revised attempt

• 1. a_r * b_r → pp1_reg
• 2. a_i * b_i → pp2_reg
• 3. pp1 – pp2 → p_r_reg

a_r * b_i → pp1_reg

• 4. a_i * b_r → pp2_reg
• 5. pp1 + pp2 → p_i_reg

 Takes 5 clock cycles

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Digital Design — Chapter 4 — Sequential Basics 8

Multiplier Control Signals

Step a_sel b_sel pp1_ce pp2_ce sub p_r_ce p_i_ce 1 1 – 2 1 1 1 – 3 1 1 1 1 4 1 1 – 5 – – 1

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Digital Design — Chapter 4 — Sequential Basics 9

Finite-State Machines

 Used the implement control sequencing  A FSM is defined by

 set of inputs  set of outputs  set of states  initial state  transition function  output function

 States are steps in a sequence of transitions

 There are “Finite” number of states.

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Digital Design — Chapter 4 — Sequential Basics 10

FSM in Hardware

 Mealy FSM: outputs depend on state and inputs  Moore FSM: outputs depend on state only (no dash)  Mealy and Moore FSM can convert to each other

Mealy FSM

• nly

D reset Q clk

current_state

• utputs

inputs clk reset

next state logic

• utput

logic

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Digital Design — Chapter 4 — Sequential Basics 11

FSM Example: Multiplier Control

 One state per step  Separate idle state?

 Wait for input_rdy = 1  Then proceed to steps 1, 2, ...  But this wastes a cycle!

 Use step 1 as idle state

 Repeat step 1 if input_rdy ≠ 1  Proceed to step 2 otherwise

 Output function

 Defined by table on slide 43  Moore or Mealy?

current_ state input_ rdy next_ state step1 step1 step1 1 step2 step2 – step3 step3 – step4 step4 – step5 step5 – step1 Transition function

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Digital Design — Chapter 4 — Sequential Basics 12

State Encoding

 Encoded in binary

 N states: use at least log2N bits

 Encoded value used in circuits for transition

and output function

 encoding affects circuit complexity

 Optimal encoding is hard to find

 CAD tools can do this well

 One-hot works well in FPGAs  Often use 000...0 for idle state

 reset state register to idle

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Digital Design — Chapter 4 — Sequential Basics 13

FSMs in Verilog

 Use parameters for state values

 Synthesis tool can choose an alternative

encoding

pa r a m a m e t e r [ 2: 0] s t e p1 = 3' b000, s t e p2 = 3' b001, s t e p3 = 3' b010, s t e p4 = 3' b011, s t e p5 = 3' b100; r e g [ 2: 0] c ur r e nt _s t a t e , ne xt _s t a t e ; . . .

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Digital Design — Chapter 4 — Sequential Basics 14

Multiplier Control in Verilog

a l wa ys @ ( pos e dge c l k or pos e dge r e s e t ) / / St a t e r e gi s t e r i f ( r e s e t ) c ur r e nt _s t a t e <= s t e p1; e l s e c ur r e nt _s t a t e <= ne xt _s t a t e ; a l wa ys @ * / / Ne xt - s t a t e l ogi c c a s e ( c ur r e nt _s t a t e ) s t e p1: i f ( ! i nput _r dy) ne xt _s t a t e = s t e p1; e l s e ne xt _s t a t e = s t e p2; s t e p2: ne xt _s t a t e = s t e p3; s t e p3: ne xt _s t a t e = s t e p4; s t e p4: ne xt _s t a t e = s t e p5; s t e p5: ne xt _s t a t e = s t e p1; e ndc a s e

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Digital Design — Chapter 4 — Sequential Basics 15

Multiplier Control in Verilog

a l wa y a l wa ys @ * be gi n e gi n / / Out put _l ogi c a _s e l = 1' b0; b_s e l = 1' b0; pp1_ce = 1' b0; pp2_c e = 1' b0; s ub = 1' b0; p_r _c e = 1' b0; p_i _ce = 1' b0; c a c a s e s e ( cur r e nt _s t a t e ) s t e p1: be gi n be gi n pp1_ce = 1' b1; e nd e nd s t e p2: be gi n be gi n a _s e l = 1' b1; b_s e l = 1' b1; pp2_ce = 1' b1; e nd e nd s t e p3: be gi n be gi n b_s e l = 1' b1; pp1_ce = 1' b1; s ub = 1' b1; p_r _ce = 1' b1; e nd e nd s t e p4: be gi n be gi n a _s e l = 1' b1; pp2_ce = 1' b1; e nd e nd s t e p5: be gi n be gi n p_i _ce = 1' b1; e nd e nd e n e ndc a s e dc a s e e nd e nd

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Digital Design — Chapter 4 — Sequential Basics 16

State Transition Diagrams

 Bubbles to represent states  Arcs to represent transitions

 Example

 S = { s1, s2, s3}  Inputs (a1, a2):

Σ = { (0,0), (0,1), (1,0), (1,1)}

 δ defined by diagram

s1 s2 s3

0, 0 0, 0 0, 1 1, 0 0, 1 1, 0 1, 1 1, 1

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Digital Design — Chapter 4 — Sequential Basics 17

State Transition Diagrams

 Annotate diagram to

define output function

 Annotate states for

Moore-style outputs

 Annotate arcs for

Mealy-style outputs

 Example

 x1, x2: Moore-style  y1, y2, y3: Mealy-style

s1 s2 s3

0, 0 / 0, 0, 0 1, 0 0, 0 0, 1 0, 0 / 0, 0, 0 0, 1 / 0, 1, 1 / 0, 1, 1 1, 0 / 1, 0, 0 0, 1 / 0, 1, 1 1, 0 / 1, 0, 0 1, 1 / 1, 1, 1 1, 1 / 1, 1, 1