EE 201: Sequential logic in VHDL Steven Bell 14 February 2019 By - PowerPoint PPT Presentation

EE 201: Sequential logic in VHDL Steven Bell 14 February 2019

By the end of class today, you should be able to: Print debugging info using report and write / writeline Use a process block for combinational logic, sequential logic, or testbench code. Create latches and fl ip- fl ops using VHDL Build counters and other simple sequential circuits in VHDL

Printing debugging info report "hello, world!"; signal a : std_logic_vector(3 downto 0); report "A is " & std_logic_vector'image(a); (concatenation) (conversion to string)

Logging to a fi le variable l : line; write(l, string'("Hello, world!")); writeline(output, l)

Process block process (SENSITIVITY) is begin -- if/case/print go here end process;

Process block process (SENSITIVITY) is begin -- if/case/print go here end process; If sensitivity includes: Combinational logic all ↕ Flip- fl op / register clk ↑ clk ↑ + data ↕ Latch Nothing Testbench (continuous evaluation) Something else Bad things you probably didn't want.

Blocking vs non-blocking Real hardware is always non-blocking! So signals/outputs must be assigned with non-blocking assignments. Intermediate variables can have blocking assignments. process(all) is variable ab : std_logic; variable notbc : std_logic; begin ab := a and b; notbc := (not b) and c; y <= ab or notbc; end

Shift register On each clock cycle, shift the input into the lowest register

Practice time http://172.104.217.120:8000/

For Tuesday 1. Read the book (3.4) and complete the pre-class quiz 2. Complete online combinational problems Submit as provide hw2_5 by 11:59pm Saturday (2/16) 3. Complete online sequential problems Submit as provide hw3 by class time Tuesday (2/19) Hangouts o ffi ce hours on Monday?