SLIDE 1
By the end of class today, you should be able to:
Use a process block for combinational logic, sequential logic,
- r testbench code.
EE 201: Sequential logic in VHDL Steven Bell 14 February 2019 By - - PowerPoint PPT Presentation
EE 201: Sequential logic in VHDL Steven Bell 14 February 2019 By - - PowerPoint PPT Presentation
EE 201: Sequential logic in VHDL Steven Bell 14 February 2019 By the end of class today, you should be able to: Print debugging info using report and write / writeline Use a process block for combinational logic, sequential logic, or testbench
SLIDE 2
SLIDE 3
Printing debugging info
report "hello, world!"; signal a : std_logic_vector(3 downto 0); report "A is " & std_logic_vector'image(a);
(concatenation) (conversion to string)
SLIDE 4
Logging to a file
variable l : line; write(l, string'("Hello, world!")); writeline(output, l)
SLIDE 5
Process block
process (SENSITIVITY) is begin
- - if/case/print go here
end process;
SLIDE 6
Process block
process (SENSITIVITY) is begin
- - if/case/print go here
end process; If sensitivity includes: all↕ clk↑ clk↑ + data↕ Nothing Something else Combinational logic Flip-flop / register Latch Testbench (continuous evaluation) Bad things you probably didn't want.
SLIDE 7
Blocking vs non-blocking
Real hardware is always non-blocking! So signals/outputs must be assigned with non-blocking assignments. Intermediate variables can have blocking assignments.
process(all) is variable ab : std_logic; variable notbc : std_logic; begin ab := a and b; notbc := (not b) and c; y <= ab or notbc; end
SLIDE 8
Shift register
On each clock cycle, shift the input into the lowest register
SLIDE 9
Practice time
http://172.104.217.120:8000/
SLIDE 10
- 1. Read the book (3.4) and complete the pre-class quiz
For Tuesday
- 2. Complete online combinational problems
Submit as provide hw2_5 by 11:59pm Saturday (2/16) Submit as provide hw3 by class time Tuesday (2/19)
- 3. Complete online sequential problems