Outline 1. Fundamental limitation of EDA software 2. Realization of - PDF document

Outline 1. Fundamental limitation of EDA software 2. Realization of VHDL operator Synthesis Of VHDL Code 3. Realization of VHDL data type 4. VHDL synthesis flow 5. Timing consideration RTL Hardware Design Chapter 6 1 RTL Hardware Design Chapter 6 2 1. Fundamental limitation Computability of EDA software • A problem is computable if an algorithm • Can “C-to-hardware” be done? exists. • EDA tools: • E.g., “halting problem”: – Core: optimization algorithms – can we develop a program that takes any – Shell: wrapping program and its input, and determines • What does theoretical computer science whether the computation of that program say? will eventually halt? – Computability • any attempt to examine the “meaning” of – Computation complexity a program is uncomputable RTL Hardware Design Chapter 6 3 RTL Hardware Design Chapter 6 4 Computation complexity Big-O notation • f(n) is O(g(n)): • How fast an algorithm can run (or how if n 0 and c can be found to satisfy: good an algorithm is)? f(n) < cg(n) for any n, n > n 0 • “Interferences” in measuring execution • g(n) is simple function: 1, n, log 2 n, n 2 , n 3 , 2 n time: • Following are O(n 2 ): – types of CPU, speed of CPU, compiler etc. RTL Hardware Design Chapter 6 5 RTL Hardware Design Chapter 6 6 1

Interpretation of Big-O E.g., • Filter out the “interference”: constants and less important terms • n is the input size of an algorithm • The “scaling factor” of an algorithm: What happens if the input size increases RTL Hardware Design Chapter 6 7 RTL Hardware Design Chapter 6 8 Theoretical limitation • Synthesis software does not know your • Intractable problems: intention – algorithms with O(2 n ) • Synthesis software cannot obtain the – Not realistic for a larger n optimal solution – Frequently tractable algorithms for sub- • Synthesis should be treated as optimal solution exist transformation and a “local search” in the • Many problems encountered in synthesis “design space” are intractable • Good VHDL code provides a good starting point for the local search RTL Hardware Design Chapter 6 9 RTL Hardware Design Chapter 6 10 2. Realization of VHDL operator • Logic operator • What is the fuss about: – Simple, direct mapping – “hardware-software” co-design? • Relational operator – SystemC, HardwareC, SpecC etc.? – =, /= fast, simple implementation exists – >, < etc: more complex implementation, larger delay • Addition operator • Other arith operators: support varies RTL Hardware Design Chapter 6 11 RTL Hardware Design Chapter 6 12 2

• Operator with one constant operand: • Operator with two constant operands: – Can significantly reduce the hardware – Simplified in preprocessing complexity – No hardware inferred – E.g., adder vs. incrementor – Good for documentation – E.g – E.g., y <= rotate_right(x, y); -- barrel shifter y <= rotate_right(x, 3); -- rewiring y <= x(2 downto 0) & x(7 downto 3); – E.g., 4-bit comparator: x=y vs. x=0 RTL Hardware Design Chapter 6 13 RTL Hardware Design Chapter 6 14 An example 0.55 um standard-cell 3. Realization of VHDL data type CMOS implementation • Use and synthesis of ‘Z’ • Use of ‘-’ RTL Hardware Design Chapter 6 15 RTL Hardware Design Chapter 6 16 • Major application: Use and synthesis of ‘Z’ – Bi-directional I/O pins – Tri-state bus • Tri-state buffer: • VHDL description: – Output with “high-impedance” y <= 'Z' when oe='1' else – Not a value in Boolean algebra a_in; – Need special output circuitry (tri-state buffer) • ‘Z’ cannot be used as input or manipulated f <= 'Z' and a; y <= data_a when in_bus='Z' else data_b; RTL Hardware Design Chapter 6 17 RTL Hardware Design Chapter 6 18 3

• Separate tri-state buffer from regular code: Bi-directional i/o pins – Less clear: with sel select y <= 'Z' when "00", '1' when "01"|"11", '0' when others ; – better: with sel select tmp <= '1' when "01"|"11", '0' when others ; y <= 'Z' when sel="00" else tmp; RTL Hardware Design Chapter 6 19 RTL Hardware Design Chapter 6 20 RTL Hardware Design Chapter 6 21 RTL Hardware Design Chapter 6 22 Tri-state bus RTL Hardware Design Chapter 6 23 RTL Hardware Design Chapter 6 24 4

Use of ‘-’ • Problem with tri-state bus – Difficult to optimize, verify and test • In conventional logic design – Somewhat difficult to design: “parking”, – ‘-’ as input value: shorthand to make table compact “fighting” – E.g., • Alternative to tri-state bus: mux RTL Hardware Design Chapter 6 25 RTL Hardware Design Chapter 6 26 – ‘-’ as output value: help simplification Use ‘-’ in VHDL – E.g., ‘-’ assigned to 1: a + b • As input value (against our intuition): ‘-’ assigned to 0: a’b + ab’ • Wrong: RTL Hardware Design Chapter 6 27 RTL Hardware Design Chapter 6 28 • Fix #1: • Wrong: • Fix #2: • Fix: RTL Hardware Design Chapter 6 29 RTL Hardware Design Chapter 6 30 5

4. VHDL Synthesis Flow • ‘-’ as an output value in VHDL • May work with some software • Synthesis: – Realize VHDL code using logic cells from the device’s library – a refinement process • Main steps: – RT level synthesis – Logic synthesis – Technology mapping RTL Hardware Design Chapter 6 31 RTL Hardware Design Chapter 6 32 RT level synthesis • Realize VHDL code using RT-level components • Somewhat like the derivation of the conceptual diagram • Limited optimization • Generated netlist includes – “regular” logic: e.g., adder, comparator – “random” logic: e.g., truth table description RTL Hardware Design Chapter 6 33 RTL Hardware Design Chapter 6 34 Module generator Logic Synthesis • “regular” logic can be replaced by pre- • Realize the circuit with the optimal number designed module of “generic” gate level components – Pre-designed module is more efficient • Process the “random” logic – Module can be generated in different levels of • Two categories: detail – Two-level synthesis: sum-of-product format – Reduce the processing time – Multi-level synthesis RTL Hardware Design Chapter 6 35 RTL Hardware Design Chapter 6 36 6

Technology mapping • E.g., • Map “generic” gates to “device-dependent” logic cells • The technology library is provided by the vendors who manufactured (in FPGA) or will manufacture (in ASIC) the device RTL Hardware Design Chapter 6 37 RTL Hardware Design Chapter 6 38 • Cost: 31 vs. 17 E.g., mapping in standard-cell ASIC • Device library RTL Hardware Design Chapter 6 39 RTL Hardware Design Chapter 6 40 E.g., mapping in FPGA Effective use of synthesis software • With 5-input LUT (Look-Up-Table) cells • Logic operators: software can do a good job • Relational/Arith operators: manual intervention needed • “layout” and “routing structure”: – Silicon chip is 2-dimensional square – “rectangular” or “tree-shaped” circuit is easier to optimize RTL Hardware Design Chapter 6 41 RTL Hardware Design Chapter 6 42 7

5. Timing consideration • Propagation delay • Synthesis with timing constraint • Hazards • Delay-sensitive design RTL Hardware Design Chapter 6 43 RTL Hardware Design Chapter 6 44 • E.g. Propagation delay • Delay: time required to propagate a signal from an input port to a output port • Cell level delay: most accurate • Simplified model: • The impact of wire becomes more dominant RTL Hardware Design Chapter 6 45 RTL Hardware Design Chapter 6 46 System delay • “False path” may exists: • The longest path (critical path) in the system • The worst input to output delay • E.g., RTL Hardware Design Chapter 6 47 RTL Hardware Design Chapter 6 48 8

Synthesis with timing constraint • RT level delay estimation: • Multi-level synthesis is flexible – Difficult if the design is mainly “random” logic • It is possible to reduce by delay by – Critical path can be identified if many complex adding extra logic operators (such adder) are used in the • Synthesis with timing constraint design. 1. Obtain the minimal-area implementation 2. Identify the critical path 3. Reduce the delay by adding extra logic 4. Repeat 2 & 3 until meeting the constraint RTL Hardware Design Chapter 6 49 RTL Hardware Design Chapter 6 50 • E.g., • Area-delay trade-off curve RTL Hardware Design Chapter 6 51 RTL Hardware Design Chapter 6 52 • Improvement in “architectural” level design Timing Hazards (better VHDL code to start with) • Propagation delay: time to obtain a stable output • Hazards: the fluctuation occurring during the transient period – Static hazard: glitch when the signal should be stable – Dynamic hazard: a glitch in transition • Due to the multiple converging paths of an output port RTL Hardware Design Chapter 6 53 RTL Hardware Design Chapter 6 54 9