Lecture 7: Sequential Networks: Registers, Finite State Machines - - PowerPoint PPT Presentation

Lecture 7: Sequential Networks: Registers, Finite State Machines

CSE 140: Components and Design Techniques for Digital Systems

Diba Mirza

• Dept. of Computer Science and Engineering

University of California, San Diego

1

D Flip-Flop (Delay)

D CLK Q Q’

Id D Q(t) Q(t+1) 0 0 0 0 1 0 1 0 2 1 0 1 3 1 1 1

Characteristic Expression Q(t+1) = D(t)

0 0 1 1 0 1 PS D 0 1 State table NS= Q(t+1)

2

What does the equation mean?

iClicker

3

How long does a D-flip flop store a bit before its

• utput can potentially change?
• A. Half a clock cycle
• B. One clock cycle
• C. Two clock cycles
• D. There is no minimum time

Rising vs. Falling Edge D Flip-Flop

4

D Q ’ Q Q ’ D Q Symbol for rising-edge triggered D flip-flop Symbol for falling-edge triggered D flip-flop

Clk

rising edges

Clk

falling edges Internal design: Just invert servant clock rather than master The triangle means clock input, edge triggered

Internal Circuit D Q CLK EN D Q 1 D Q EN Symbol

• Inputs: CLK, D, EN

– The enable input (EN) controls when new data (D) is stored

• Function

– EN = 1: D passes through to Q on the clock edge – EN = 0: the flip-flop retains its previous state

Enabled D-FFs

6

Bit Storage Overview

7

D flip-flop D latch master D latch servant Dm Qm C m Ds D Clk Qs’ Cs Qs Q ’ Q S R D Q C D latch

Only loads D value present at rising clock edge, so values can’t propagate to other flip- flops during same clock cycle. Tradeoff: uses more gates internally than D latch, and requires more external gates than SR – but gate count is less of an issue today. SR can’t be 11 if D is stable before and while C=1, and will be 11 for only a brief glitch even if D changes while C=1. Problem: C=1 too long propagates new values through too many latches: too short may not enable a store.

S1 R1 S Q C R Level-sensitive SR latch

S and R only have effect when C=1. We can design outside circuit so SR=11 never happens when C=1. Problem: avoiding SR=11 can be a burden.

R (reset) S (set) Q SR latch

S=1 sets Q to 1, R=1 resets Q to 0. Problem: SR=11 yield undefined Q.

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Shift register

• Holds & shifts samples of input

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D Q D Q D Q D Q IN OUT1 OUT2 OUT3 OUT4 CLK

Pattern Recognizer

• Combinational function of input samples

10

D Q D Q D Q D Q IN OUT1 OUT2 OUT3 OUT4 CLK OUT

Counters

11

D Q D Q D Q D Q IN OUT1 OUT2 OUT3 OUT4 CLK

• Sequences through a fixed set of patterns

What we will learn:

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• 1. Describe the desired behavior of a sequential circuit over time

(FSMs)

• 2. Given the behavior of a sequential circuit, implement the circuit

Wall-E is a Finite State Machine

Active Inactive

Describing Wall-E Implementing Wall-E

Finite State Machines: Describing circuit behavior over time

13

2 bit Counter Symbol/ Circuit

Finite State Machines: Describing circuit behavior over time

14

Free running 2 bit Counter Symbol/ Circuit Output over time time

CLK Q1 Q0

What is the expected output of the counter over time?

Finite State Machines: Describing circuit behavior over time

15

2 bit Counter 00 Symbol/ Circuit Diagram that depicts behavior over time 01 10 11

State: What is it ? Why do we need it?

16

Symbol/ Circuit Behavior over time time

CLK

2 bit Counter PI Q: At time t1, what information is needed to produce the output of the counter at the next rising edge of the clock (i.e t2)?

• A. All the outputs of the counter until t1
• B. The initial output of the counter at time t=0
• C. The output of the counter at current time t1
• D. We cannot determine the output of the counter at t2 prior to t2

t1 t2

Implementing the 2 bit counter

17

S0 S1 S2 S3

State Diagram State Table

Q1(t) Q0(t) Q1(t+1) Q0(t+1) Current state Next State S0 S1 S1 S2 S2 S3 S3 S0

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State Table

Q1(t) Q0(t) Q1(t+1) Q0(t+1) 1 1 1 1 1 1 1 1

PI Q: Which of the following is the likely structure of the circuit realization of the counter Q0(t) Q1(t)

D Q Q’ D Q Q’

CLK Circuit with 2 flip flops B.

Combinational circuit Combinational circuit

Circuit with no flip flops A.

Q0(t) Q1(t)

Q D Q Q’

CLK Circuit with one flip flop C.

Combinational circuit

19

State Table

Q1(t) Q0(t) Q1(t+1) Q0(t+1) 1 1 1 1 1 1 1 1

Q0(t) Q1(t)

D Q Q’ D Q Q’

CLK Circuit with 2 flip flops B.

Combinational circuit D0(t) = Q0(t)’ D1(t) = Q0(t) Q1(t)’ + Q0(t)’ Q1(t)

20

State Table

Q1(t) Q0(t) Q1(t+1) Q0(t+1) 1 1 1 1 1 1 1 1

We store the current state using D-flip flops so that:

• Inputs to the combinational circuit

don’t change while the next output is being computed

• The transition to the next state
• nly occurs at the rising edge of

the clock Q0(t) Q1(t)

D Q Q’ D Q Q’

CLK Implementation of 2-bit counter

Q0(t+1) = Q0(t)’ Q1(t+1) = Q0(t) Q1(t)’ + Q0(t)’ Q1(t)

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Generalized Model of Sequential Circuits

S(t) X Y CLK

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Mealy Machine: yi(t) = fi(X(t), S(t)) Moore Machine: yi(t) = fi(S(t)) si(t+1) = gi(X(t), S(t)) C1 C2

CLK x(t) y(t)

Mealy Machine

S(t)

C1 C2

CLK x(t) y(t)

Moore Machine

S(t)

Canonical Form: Mealy and Moore Machines

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C1 C2

CLK x(t) y(t)

Mealy Machine C1 C2

CLK x(t) y(t)

Moore Machine

S(t) S(t)

Differences in State Diagram: Mealy vs. Moore Machines

This Counter Design Is:

• A. Moore machine
• B. Mealy machine
• C. None of the above

D Q D Q D Q OUT1 OUT2 OUT3 CLK "1"

Life on Mars?

25

This pattern recognizer should have

• A. One state because it has one output
• B. One state because it has one input
• C. Two states because the input can be 0 or 1
• D. More than two states because ….
• E. None of the above

Mars rover has a binary input x. When it receives the input sequence x(t-2, t) = 001 from its life detection sensors, it means that the it has detected life on Mars J and the output y(t) = 1, otherwise y(t) = 0 (no life on Mars L).

Life on Mars?

26

Mars rover has a binary input x. When it receives the input sequence x(t-2, t) = 001 from its life detection sensors, it means that the it has detected life on Mars J and the output y(t) = 1, otherwise y(t) = 0 (no life on Mars L).

Mars Life Recognizer FSM

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S1 S0

0/0 1/0 0/0 1/1

S2

0/0 1/0

Which of the following diagrams is a correct Mealy solution for the 001 pattern recognizer on the Mars rover?

A.

S1 S0

0/0 1/0 1/0 0/0

S2

1/1 B. 0/0

• C. Both A and B are correct
• D. None of the above

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Pattern Recognizer ‘001’

S1 S0

0/0 1/0 0/0 1/1

S2

0/0 1/0

C1 C2

CLK x(t) y(t)

Mealy Machine

S(t)

What does state table need to show to design controls of C1?

• A. (current input x(t), current state S(t) vs. next state, S(t+1))
• B. (current input, current state vs. current output y(t))
• C. (current input, current state vs. current output, next state)
• D. None of the above

Mars Life Recognizer FFs

29

State Diagram => State Table with State Assignment

State Assignment S0: 00 S1: 01 S2: 10

S(t)\x 1 S0 S1,0 S0,0 S1 S2,0 S0,0 S2 S2,0 S0,1

S(t)\x 1 00 01,0 00,0 01 10,0 00,0 10 10,0 00,1 Q1(t+1)Q0(t+1), y

C1 C2

CLK x(t) y(t)

Mealy Machine

S(t)

S1 S0

0/0 1/0 0/0 1/1

S2

0/0 1/0

30

State Diagram => State Table => Excitation Table => Circuit

Q1(t) Q0(t)\x 0 1 00 01,0 00,0 01 10,0 00,0 10 10,0 00,1

id Q1Q0x D1 D0 y 000 1 1 001 2 010 1 3 011 4 100 1 5 101 1 6 110 X X X 7 111 X X X C1 C2

CLK x(t) y(t)

Mealy Machine

S(t)

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0 2 6 4 1 3 7 5

x(t) Q1

0 1 X 1 0 0 X 0

Q0

D1(t): D1(t) = x’Q0 + x’Q1 D0 (t)= Q’1Q’0 x’ y= Q1x

State Diagram => State Table => Excitation Table => Circuit

id Q1Q0x D1 D0 y 000 1 1 001 2 010 1 3 011 4 100 1 5 101 1 6 110 X X X 7 111 X X X

32

D1(t) = x’Q0 + x’Q1 D0 (t)= Q’1Q’0 x’ y= Q1x

D Q Q’ D Q Q’

Q1 Q0 D1 D0 Q0 Q1 x’ x y Q’1 Q’0 x’

State Diagram => State Table => Excitation Table => Circuit

C1 C2

CLK x(t) y(t)

Mealy Machine

S(t)

Moore FSM for the Mars Life Recognizer

33

S1 S0

0/0 1/0 0/0 1/1

S2

0/0 1/0 Which of the following diagrams is a correct Moore solution to the ‘001’ pattern recognizer? A. B.

• C. Both A and B are correct
• D. None of the above

S1 S0

1 1

S2

1

S3 1

1

Moore Mars Life Recognizer: FF Input Specs

34

Pattern Recognizer ‘001’

What does state table need to show to design controls of C2?

• A. (current input x(t), current state S(t) vs. next state, S(t+1))
• B. (current input, current state vs. current output y(t))
• C. (current state vs. current output y(t) and next state)
• D. (current state vs. current output y(t) )
• E. None of the above

C1 C2

CLK x(t) y(t)

Moore Machine

S(t)

S1 S0

1 1

S2

1

S3 1

1

Q1Q0\x 1 00 01,0 00,0 01 10,0 00,0 10 10,0 11,0 11 01,1 00,1 Q1(t+1)Q0(t+1), y

ID Q1Q0x D1 D0 y 000 1 1 001 2 010 1 3 011 4 100 1 5 101 1 1 6 110 1 1 7 111 1

S(t)\x 1 S0 S1,0 S0,0 S1 S2,0 S0,0 S2 S2,0 S3,0 S3 S1,1 S0,1

Moore Mars Life Recognizer: State Table

S1 S0

1 1

S2

1

S3 1

1

id Q1Q0x D1 D0 y 000 1 1 001 2 010 1 3 011 4 100 1 5 101 1 1 6 110 1 1 7 111 1

0 2 6 4 1 3 7 5

x(t) Q1

1 0 1 0 0 0 0 1

Q0

D0(t):

0 2 6 4 1 3 7 5

x(t) Q1

0 1 0 1 0 0 0 1

Q0

D1(t):

0 2 6 4 1 3 7 5

x(t) Q1

0 0 1 0 0 0 1 0

Q0

y(t):

Mars Life Recognizer: Combinational Circuit Design

Mars Life Recognizer Circuit Implementation

37

D Q Q’ D Q Q’

Q1 Q0 D1 D0 y

State Diagram => State Table => Excitation Table => Circuit

C1 C2

CLK x(t) y(t)

Moore Machine

S(t)