Lecture 7: Sequential Networks: Registers, Finite State Machines - PowerPoint PPT Presentation

Lecture 7: Sequential Networks: Registers, Finite State Machines CSE 140: Components and Design Techniques for Digital Systems Diba Mirza Dept. of Computer Science and Engineering 1 University of California, San Diego

D Flip-Flop (Delay) Id D Q(t) Q(t+1) Q D 0 0 0 0 1 0 1 0 CLK 2 1 0 1 Q’ 3 1 1 1 State table Characteristic Expression Q(t+1) = D(t) PS D 0 1 0 0 1 What does the equation mean? 1 0 1 NS= Q(t+1) 2

iClicker How long does a D-flip flop store a bit before its output can potentially change? A. Half a clock cycle B. One clock cycle C. Two clock cycles D. There is no minimum time 3

Rising vs. Falling Edge D Flip-Flop D D Q ’ Q ’ Internal design: The triangle Just invert servant Q Q means clock clock rather than input, edge master triggered Symbol for rising-edge Symbol for falling-edge triggered D flip-flop triggered D flip-flop rising edges falling edges Clk Clk 4

Enabled D-FFs • Inputs: CLK , D , EN – The enable input ( EN ) controls when new data ( D ) is stored • Function – EN = 1: D passes through to Q on the clock edge – EN = 0: the flip-flop retains its previous state Internal Circuit Symbol EN CLK 0 D Q Q D Q D 1 EN

6

Bit Storage Overview SR latch Level-sensitive SR latch D latch D flip-flop S (set) S D S1 S D latch D latch Q ’ D Dm Qm Ds Qs’ C C Q C m Cs Qs Q Q Q master servant R Clk R R1 R (reset) S=1 sets Q to 1, S and R only have effect SR can’t be 11 if D is Only loads D value present at R=1 resets Q to 0. when C=1. We can stable before and while rising clock edge, so values Problem: SR=11 design outside circuit so C=1, and will be 11 for only can’t propagate to other flip- yield undefined Q. SR=11 never happens a brief glitch even if D flops during same clock cycle. when C=1. Problem: changes while C=1. Tradeoff: uses more gates avoiding SR=11 can be a Problem: C=1 too long internally than D latch, and burden. propagates new values requires more external gates through too many latches: than SR – but gate count is less of an issue today. too short may not enable a store. 7

8

Shift register • Holds & shifts samples of input OUT1 OUT2 OUT3 OUT4 D Q D Q D Q D Q IN CLK 9

Pattern Recognizer • Combinational function of input samples OUT OUT1 OUT2 OUT3 OUT4 D Q D Q D Q D Q IN CLK 10

Counters • Sequences through a fixed set of patterns OUT1 OUT2 OUT3 OUT4 D Q D Q D Q D Q IN CLK 11

What we will learn: 1. Describe the desired behavior of a sequential circuit over time (FSMs) 2. Given the behavior of a sequential circuit, implement the circuit Describing Wall-E Wall-E is a Finite State Machine Inactive Active 12 Implementing Wall-E

Finite State Machines: Describing circuit behavior over time Symbol/ Circuit 2 bit Counter 13

Finite State Machines: Describing circuit behavior over time Output over time Symbol/ Circuit CLK time Free running 2 bit Counter Q 1 Q 0 What is the expected output of the counter over time? 14

Finite State Machines: Describing circuit behavior over time Diagram that depicts Symbol/ Circuit behavior over time 00 2 bit Counter 01 11 10 15

State: What is it ? Why do we need it? Symbol/ Circuit Behavior over time CLK 2 bit Counter t 1 t 2 time PI Q: At time t 1 , what information is needed to produce the output of the counter at the next rising edge of the clock (i.e t 2 )? A. All the outputs of the counter until t 1 B. The initial output of the counter at time t=0 C. The output of the counter at current time t 1 D. We cannot determine the output of the counter at t 2 prior to t 2 16

Implementing the 2 bit counter S 0 Current state Next State S 0 S 1 S 1 S 2 S 3 S 1 S 2 S 3 S 3 S 0 S 2 Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1) State Diagram State Table 17

State Table PI Q: Which of the following is the likely structure of the circuit realization of the Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1) counter 0 0 0 1 A. 0 1 1 0 Combinational 1 0 1 1 circuit 1 1 0 0 Circuit with no flip flops Q B. C. D Q’ Q 0 (t) Q Combinational Q Q 0 (t) circuit D Combinational Q’ Q Q 1 (t) circuit D Q’ CLK Q 1 (t) CLK Circuit with 2 flip flops 18 Circuit with one flip flop

State Table Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1) 0 0 0 1 D 0 (t) = Q 0 (t)’ D 1 (t) = Q 0 (t) Q 1 (t)’ + Q 0 (t)’ Q 1 (t) 0 1 1 0 1 0 1 1 1 1 0 0 Q B. D Q’ Q 0 (t) Combinational Q circuit D Q 1 (t) Q’ CLK Circuit with 2 flip flops 19

Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1) Q 0 (t+1) = Q 0 (t)’ 0 0 0 1 Q 1 (t+1) = Q 0 (t) Q 1 (t)’ + Q 0 (t)’ Q 1 (t) 0 1 1 0 1 0 1 1 1 1 0 0 State Table Q We store the current state using D-flip D flops so that: Q’ Q 0 (t) • Inputs to the combinational circuit Q don’t change while the next output D Q’ is being computed Q 1 (t) • The transition to the next state CLK only occurs at the rising edge of the clock Implementation of 2-bit counter 20

Generalized Model of Sequential Circuits Y X S(t) CLK 21

Canonical Form: Mealy and Moore Machines Mealy Machine: y i (t) = f i (X(t), S(t)) Moore Machine: y i (t) = f i (S(t)) s i (t+1) = g i (X(t), S(t)) x(t) x(t) y(t) y(t) C1 C2 C1 C2 CLK CLK S(t) S(t) Moore Machine Mealy Machine 22

Differences in State Diagram: Mealy vs. Moore Machines x(t) x(t) y(t) C1 C2 y(t) C1 C2 CLK CLK S(t) S(t) Moore Machine Mealy Machine 23

This Counter Design Is: A. Moore machine B. Mealy machine C. None of the above OUT1 OUT2 OUT3 D Q D Q D Q CLK "1"

Life on Mars? Mars rover has a binary input x. When it receives the input sequence x(t-2, t) = 001 from its life detection sensors, it means that the it has detected life on Mars J and the output y(t) = 1, otherwise y(t) = 0 (no life on Mars L ). This pattern recognizer should have A. One state because it has one output B. One state because it has one input C. Two states because the input can be 0 or 1 D. More than two states because …. E. None of the above 25

Life on Mars? Mars rover has a binary input x. When it receives the input sequence x(t-2, t) = 001 from its life detection sensors, it means that the it has detected life on Mars J and the output y(t) = 1, otherwise y(t) = 0 (no life on Mars L ). 26

Mars Life Recognizer FSM Which of the following diagrams is a correct Mealy solution for the 001 pattern recognizer on the Mars rover? 1/1 A. 1/0 0/0 0/0 S1 S0 S2 0/0 1/0 B. 0/0 1/0 0/0 1/1 S0 S1 S2 1/0 C. Both A and B are correct 0/0 27 D. None of the above

Mars Life Recognizer FFs Pattern Recognizer ‘001’ x(t) 1/1 1/0 y(t) C1 C2 0/0 0/0 S0 S1 S2 0/0 CLK S(t) 1/0 Mealy Machine What does state table need to show to design controls of C1? A. (current input x(t), current state S(t) vs. next state, S(t+1)) B. (current input, current state vs. current output y(t)) C. (current input, current state vs. current output, next state) D. None of the above 28

State Diagram => State Table with State Assignment x(t) 1/1 1/0 y(t) C1 C2 0/0 0/0 S0 S1 S2 0/0 CLK S(t) 1/0 Mealy Machine State Assignment S(t)\x 0 1 S(t)\x 0 1 S0: 00 S0 S1,0 S0,0 00 01,0 00,0 S1: 01 01 10,0 00,0 S1 S2,0 S0,0 S2: 10 10 10,0 00,1 S2 S2,0 S0,1 Q 1 (t+1)Q 0 (t+1), y 29

State Diagram => State Table => Excitation Table => Circuit id Q 1 Q 0 x D 1 D 0 y Q 1 (t) Q 0 (t)\x 0 1 00 01,0 00,0 000 0 0 1 0 01 10,0 00,0 001 1 0 0 0 10 10,0 00,1 010 2 1 0 0 011 x(t) 3 0 0 0 100 4 1 0 0 y(t) C1 C2 101 5 0 0 1 CLK 110 6 X X X S(t) Mealy Machine 111 7 X X X 30

State Diagram => State Table => Excitation Table => Circuit Q 0 id Q 1 Q 0 x D 1 D 0 y D 1 (t): 0 2 6 4 000 0 0 1 0 0 1 X 1 001 1 3 7 5 1 0 0 0 0 0 X 0 x(t) 010 2 1 0 0 Q 1 011 3 0 0 0 D 1 (t) = x’Q 0 + x’Q 1 100 4 1 0 0 D 0 (t)= Q’ 1 Q’ 0 x’ 101 5 0 0 1 y= Q 1 x 110 6 X X X 111 7 X X X 31

State Diagram => State Table => Excitation Table => Circuit Q’ 1 Q 0 D 0 Q Q’ 0 D x’ Q’ Q 1 y x’ D 1 Q D Q 0 Q’ Q 1 x x(t) y(t) C1 C2 D 1 (t) = x’Q 0 + x’Q 1 D 0 (t)= Q’ 1 Q’ 0 x’ CLK y= Q 1 x S(t) Mealy Machine 32

Moore FSM for the Mars Life Recognizer Which of the following diagrams is a correct Moore solution to the ‘001’ pattern recognizer? 1/1 1/0 A. 0/0 0/0 S0 S1 S2 0/0 B. 1/0 1 0 1 1 0 0 S0 S1 S2 S3 0 0 0 1 1 0 C. Both A and B are correct D. None of the above 33

Moore Mars Life Recognizer: FF Input Specs Pattern Recognizer ‘001’ x(t) y(t) C1 C2 1 0 1 1 0 0 S0 S1 S2 S3 CLK 0 0 0 1 S(t) 1 0 Moore Machine What does state table need to show to design controls of C2? A. (current input x(t), current state S(t) vs. next state, S(t+1)) B. (current input, current state vs. current output y(t)) C. (current state vs. current output y(t) and next state) D. (current state vs. current output y(t) ) E. None of the above 34