Chapter 3 Registers, Counters, Shift Registers Process Control - - PDF document

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Dec 22, 2022 113 likes •191 views

Chapter 3 Registers, Counters, Shift Registers Process Control Flaxer Eli - Process Control Ch 3 - 1 MSI Quad Registers 74LS175 1Q 1D Q D Q /1Q CLR 74LS175 CLK 2Q 2D Q CLR D Q /2Q CLR 1D 1Q 1Q 3Q 2D 2Q 3D Q D 2Q Q

SLIDE 1

Flaxer Eli - Process Control

Ch 3 - 1

Chapter 3

Process Control

Registers, Counters, Shift Registers

Flaxer Eli - Process Control

Ch 3 - 2

MSI Quad Registers

CLK CLR 4Q 4Q 3Q 3Q 2Q 2Q 1Q 1Q

74LS175

1D 2D 3D 4D

JAL

CLR Q Q

/1Q 1D

CLR Q Q

/2Q 2D

CLR Q Q

/3Q 3D

CLR Q Q

/4Q 4D CLK /CLR

74LS175

SLIDE 2

Flaxer Eli - Process Control

Ch 3 - 3

Octal Register with Clock Enable

CLK G

74LS377

1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q

JAL

Flaxer Eli - Process Control

Ch 3 - 4

74163 4-bit Synchronous Parallel Counter

>CLK CLR LD ENP ENT A B C D QA QB QC QD RCO

74X163

CLT

LSB MSB RCO = Ripple Carry Out, when Count = 1111 and ENT = 1 Common Clock Synchronous Clear Synchronous Load Count Enable = ENP • ENT Load Data Inputs

SLIDE 3

Flaxer Eli - Process Control

Ch 3 - 5

74163 State Table

Inputs Current State Next State /CLR /LD ENT ENP QD QC QB QA QD* QC* QB* QA* 0 X X X

1 0 X X 1 1 0 X 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

X X X X

X X X X X X X X X X X X 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1

0 0 0 0

D C B A QD QC QB QA QD QC QB QA 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0

CLT

Clear Load Hold Hold Count . . .

Flaxer Eli - Process Control

Ch 3 - 6

Application - Free Running Modulo-16 Counter

CLT

>CLK CLR LD ENP ENT A B C D QA QB QC QD RCO

74X163 CLOCK +5 V R

Q0 Q1 Q2 Q3

SLIDE 4

Flaxer Eli - Process Control

Ch 3 - 7

Modulo-11 Counter [5,6, …, 15, 5, 6, ...]

When Count=15 ➙ Load 5 (0101) Any Modulus 2 ➙ 16 possible

CLT

>CLK CLR LD ENP ENT A B C D QA QB QC QD RCO

74X163 CLOCK +5 V CNT15 /CNT15

Q0 Q1 Q2 Q3

1 1

Flaxer Eli - Process Control

Ch 3 - 8

Modulo-11 Counter [0,1,2, …, 10, 0, 1, ...]

When Count=10 ➙ Clear Decode Count 1x1x (10…15) ➯ Q3 • Q1

CLT

>CLK CLR LD ENP ENT A B C D QA QB QC QD RCO

74X163 CLOCK +5 V

Q0 Q1 Q2 Q3

+5 V

SLIDE 5

Flaxer Eli - Process Control

Ch 3 - 9

74169 Up/Down Counter

UP/DN = 1 = up ➙ RCO = 15 UP/DN = 0 = down ➙ RCO = 0 up down up Ex: 0,1,2, 1,0,15,14, 15,0,1,2 RCO RCO

>CLK UP/DN LD ENP ENT A B C D QA QB QC QD RCO

74X169

CLT

Flaxer Eli - Process Control

Ch 3 - 10

Shift Registers

X 0 1 1 1 Q1 Q2 Q3 Q4 Shift Right X 0 1 1 Q1 Q2 Q3 Q4 0 1 1 1 Y Q1 Q2 Q3 Q4 Shift Left 1 1 1 Y Q1 Q2 Q3 Q4 Often used to rearrange bits or Multiply/Divide by 2

Multi-bit register that moves data “sideways” left/right ( 1 bit/clock )

SLIDE 6

Flaxer Eli - Process Control

Ch 3 - 11

MSI Shift Registers

CLK

CLR SERA SERB QA QB QC QD QE QF QG QH

8 9 1 2 3 4 6 5 10 12 13 11

74X164

Octal (8-bit) SIPO Async And’ed

CLK CLKINH SH/LD CLR SER A B C D E F G H QH

7 15 6 9 1 2 3 4 5 10 11 12 13

74X166

Octal (8-bit) SISO, PISO