Octal Tri-state Register/Latch Counters 74LS374 CLK 74LS374 OE - - PDF document

SLIDE 1

Flaxer Eli - Logic Design

Ch 9 - 1

Octal Tri-state Register/Latch

CLK OE

74LS374

1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q C OE

74LS373

1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q

JAL

1Q 2Q 8Q

D Q D Q D Q

1D 2D 8D /OE CLK

74LS374

Flaxer Eli - Logic Design

Ch 9 - 2

Counters

• Clocked sequential circuit with single-cycle state diagram

– Modulo-m counter = divide-by-m counter

• Most Common:

n-bit binary counter, where m = 2n ➙ n flip-flops, counts 0 … 2n-1

S3 S2 S1 Sm

CLT

Flaxer Eli - Logic Design

Ch 9 - 3

Synchronous Parallel Counter

• Single-level enable

logic per flip-flop

• Fastest and most

complex type of counter

• Requires ∆ t < TCLK
• All outputs change

simultaneously tCQ after CLK >T Q EN >T Q EN >T Q EN >T Q EN CLK CNTEN Q0 Q1 Q2 Q3

CLT

Equation? Delay?

Flaxer Eli - Logic Design

Ch 9 - 4

74163 4-bit Synchronous Parallel Counter

>CLK CLR LD ENP ENT A B C D QA QB QC QD RCO

74X163

CLT

LSB MSB RCO = Ripple Carry Out, when Count = 1111 and ENT = 1

(74161 is the same, but with an asynchronous clear)

Common Clock Synchronous Clear Synchronous Load Count Enable = ENP • ENT Load Data Inputs

Flaxer Eli - Logic Design

Ch 9 - 5

74163 State Table

Inputs Current State Next State /CLR /LD ENT ENP QD QC QB QA QD* QC* QB* QA* 0 X X X

1 0 X X 1 1 0 X 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

X X X X

X X X X X X X X X X X X 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1

0 0 0 0

D C B A QD QC QB QA QD QC QB QA 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0

CLT

Clear Load Hold Hold Count . . .

Flaxer Eli - Logic Design

Ch 9 - 6

CLK QA QB QC QD RCO

COUNT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

CLT

(Div2) (Div4) (Div8) (Div16)

Free-Running Modulo-16 Counter Timing Diagram

SLIDE 2

Flaxer Eli - Logic Design

Ch 9 - 7

Modulo-11 Counter [5,6, …, 15, 5, 6, ...]

>CLK CLR LD ENP ENT A B C D QA QB QC QD RCO

74X163 CLOCK +5 V CNT15 /CNT15

Q0 Q1 Q2 Q3

When Count=15 ➙ Load 5 (0101) Any Modulus 2 ➙ 16 possible

CLT

1 1

Flaxer Eli - Logic Design

Ch 9 - 8

Decoded Modulo-8 Counter

>CLK CLR LD ENP ENT A B C D QA QB QC QD RCO

74X163 +5 V R

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 G1 G2A G2B

CLOCK 74X138

/S0 /S1 /S2 /S3 /S4 /S5 /S6 /S7

CLT

Only

• ne
• utput

true per state Better Solution: Ring Counter Less logic, simpler to understand

Flaxer Eli - Logic Design

Ch 9 - 9

Shift Registers

X 0 1 1 1 Q1 Q2 Q3 Q4 Shift Right X 0 1 1 Q1 Q2 Q3 Q4 0 1 1 1 Y Q1 Q2 Q3 Q4 Shift Left 1 1 1 Y Q1 Q2 Q3 Q4 Often used to rearrange bits or Multiply/Divide by 2

JZ

• Multi-bit register that moves data “sideways” left/right ( 1 bit/clock )

Flaxer Eli - Logic Design

Ch 9 - 10

Serial In, Parallel Out (SIPO) Shift register

D Q CLK D Q CLK D Q CLK

• SERIN

CLOCK NQ 2Q 1Q

JZ

Serial to Parallel Converter 4-bit shift register example: serin: 1 0 1 1 0 0 1 1 1 0 1Q: - 1 0 1 1 0 0 1 1 1 2Q: - - 1 0 1 1 0 0 1 1 3Q: - - - 1 0 1 1 0 0 1 4Q: - - - - 1 0 1 1 0 0 clock:

Flaxer Eli - Logic Design

Ch 9 - 11

Parallel In, Parallel Out (PIPO) Shift Register

JZ

SERIN CLOCK

D Q CLK D Q CLK D Q CLK

• LOAD/SHIFT

1D 2D ND 1Q 2Q NQ S L S L S L General Purpose: Makes any kind

• f shift register!

Flaxer Eli - Logic Design

Ch 9 - 12

MSI Shift Registers

JZ

CLK

CLR SERA SERB QA QB QC QD QE QF QG QH

8 9 1 2 3 4 6 5 10 12 13 11

74X164

Octal (8-bit) SIPO Async And’ed

CLK CLKINH SH/LD CLR SER A B C D E F G H QH

7 15 6 9 1 2 3 4 5 10 11 12 13

74X166

Octal (8-bit) SISO, PISO

SLIDE 3

Flaxer Eli - Logic Design

Ch 9 - 13

MSI Shift Registers

CLK CLR S1 S0 LIN D QD C QC B QB A QA RIN

11 1 10 9 7 6 4 5 3 2 12 13 14 15

74X194

JZ

Quad Bidirectional Universal (4-bit) PIPO Modes: Hold Load Shift Right Shift Left R L

Flaxer Eli - Logic Design

Ch 9 - 14

74x194 State table (4 functions)

Input Next state Function S1 S0 QA* QB* QC* QD* Hold 0 0 QA QB QC QD Shift right 0 1 RIN QA QB QC Shift left 1 0 QB QC QD LIN Load 1 1 A B C D

JZ

Flaxer Eli - Logic Design

Ch 9 - 15

74x194 Schematic

CLK /CLR LIN D C

(11) (1) (7) (6) (5)

D Q CLK CLR D Q CLK CLR

10 00 11 01 01 11 00 10 (12) (13)

QD QC RIGHT

S1 S0

Bidirectional = Shift Left(QA QD) / Right (QA QD)

JZ

SL HO LD SR

LEFT Flaxer Eli - Logic Design

Ch 9 - 16

Universal shift register

D Q CLK CLR D Q CLK CLR

10 00 11 01 01 11 00 10 (14) (15)

QB QA LEFT

(4)

B S1 S0 A RIN

(10) (9) (3) (2) JZ

RIGHT Flaxer Eli - Logic Design

Ch 9 - 17

Shift Register Control Application: Ring Counter

• Shift Register Counter

– cyclic state diagram – not normal counting sequence

• Ring Counter

– n states with n-bit Shift Register – simplest form – initially reset to load 0001 => QABCD

• Glitch-free 1-of-n decoder

(cheap)

0001 0001 0010 0100 1000 Repeating

CLT

RIN A B C D LIN S0 S1 CLR CLK +5 V R 74X194 CLOCK RESET QA QB QC QD Wired as a shift-left shift register Q0 Q1 Q2 Q3 Flaxer Eli - Logic Design

Ch 9 - 18

Ring Counter Timing

CLOCK Q0 Q1 Q2 Q3 RESET

CLT

Load Shift