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Jan 01, 2023 312 likes •583 views

Paper presentation Ultra-Portable Devices Paper: Shanti Pavan, Nagendra Krishnapura, et al. A Power Optimized Continuous- Time ADC for Audio Applications, Journal of Solid State Circuits, Vol. 43, No. 2, pp 351-360, Feb 2008. Presented

SLIDE 1

Paper presentation – Ultra-Portable Devices

Paper: Presented by:

Shanti Pavan, Nagendra Krishnapura, et al. A Power Optimized Continuous-Time Δ∑ ADC for Audio Applications, Journal of Solid State Circuits, Vol. 43,

No. 2, pp 351-360, Feb 2008.

Dejan Radjen

2010-03-23 1 Paper Presentation - Ultra Portable Devices

SLIDE 2

Outline

Introduction
Choice of Architecture
Circuit Design
Measurement Results
Summary and Conclusions

2010-03-23 2 Paper Presentation - Ultra Portable Devices

SLIDE 3

Introduction

Traditional Δ∑-modulators were discrete time designs
Continuous time Δ∑-modulators offer following advantages

– Implicit anti alias filtering – More relaxed amplifier GBW-requirements

Several strategies employed to reduce power consumption

– Large input signal (3 V p-p differential) – Chosen NTF results in performance tolerant against comparator offsets – Excess delay compensation

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SLIDE 4

Choice of Architecture

A single loop topology is chosen
The 3:rd order NTF chosen ensures an SQNR well above 92 dB

(in a 24 kHz bandwidth)

Resulting SQNR ensures that the design is limited by thermal

noise

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SLIDE 5

Choice of Architecture

Multi bit vs. single bit quantizer

Lower in-band quantization noise
Lower noise due to clock jitter
Lower slew rate requirements in the loop filter

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SLIDE 6

Choice of Architecture

Choosing the Noise Transfer Function

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SLIDE 7

Choice of Architecture

Choosing the Noise Transfer Function

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SLIDE 8

Choice of Architecture

Effect of systematic RC time-constant deviation

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SLIDE 9

Choice of Architecture

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Feed forward Distributed feedback

Modulator architectures

SLIDE 10

Circuit Design

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Loop Filter

Summing Amplifier

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Circuit Design

Poles in the opamps introduce excess delay in the loop filter
If the feedback pulse ends outside the clock cycle, the order of the

system is increased

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Excess loop delay

SLIDE 12

Circuit Design

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Conventional excess delay compensation

SLIDE 13

Circuit Design

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Proposed excess delay compensation

SLIDE 14

Circuit Design

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Opamp for the first integrator

SLIDE 15

Circuit Design

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Opamp for the rest of the integrators

SLIDE 16

Circuit Design

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Block diagram of the quantizer

SLIDE 17

Circuit Design

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Comparator schematic and timing

SLIDE 18

Circuit Design

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Effect of comparator random offset on SNDR

SLIDE 19

Circuit Design

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Digital back-end and DEM logic

SLIDE 20

Circuit Design

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Implementation of the DAC-cell

SLIDE 21

Measurement Results

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SNR, SNDR and dynamic range

SLIDE 22

Measurement Results

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Output spectrum

SLIDE 23

Measurement Results

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Figure of merit

SLIDE 24

Measurement Results

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SLIDE 25

Measurement Results

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SLIDE 26

Summary and Conclusions

A CT Δ∑ - modulator with a multi bit quantizer was designed to

improve on the single bit modulators

NTF was chosen to achieve a design immune to RC – time

constant variation, jitter and comparator offsets

Several measures were taken to reduce power consumption
A new compensation technique was used to compensate for

excess loop delay

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