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Paper presentation Ultra-Portable Devices Paper: CH. Winstead, N. Nguyen, V. Gaudet, CH. Schlegel. Low-Voltage CMOS Circuits for Analog Iterative Decoders. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, REGULAR PAPERS, vol. 53, no. 4, April

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Paper presentation Ultra-Portable Devices

Paper: Presented by:

CH. Winstead, N. Nguyen, V. Gaudet, CH. Schlegel.

Low-Voltage CMOS Circuits for Analog Iterative Decoders.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, REGULAR PAPERS, vol. 53, no. 4, April 2006, pages 829-841. Reza Meraji

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Outline

Decoding Circuits based on sum-product algorithm

Canonical topology Low voltage topology

Decoder architectures

Trellis Tanner Graph

Example decoder implementations Performance results

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Sum-Product Algorithm

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Canonical Sum-Product Circuit

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Canonical Sum-Product Circuit:

Source Connected Transistor Array

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Re-normalization Circuit

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A Slice of the Canonical Topology

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Low Voltage Sum-Product Circuit Topology

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Allowable Supply Voltages

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Difference in Minimum Supply Voltage

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Decoder Architectures:

Trellis Decoders (Hamming Code)

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Low-Voltage Circuit for Trellis Decoding

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LDPC (Tanner Graph) Decoders

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Tanner graph for an (8,4) Hamming code Implementation of equality and parity-check nodes for LDPC-style decoders

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Die micro photograph of chip:

showing the factor graph decoder , the Trellis decoder, and the I/O interfaces

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Decoder Implementations Summary

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Serial I/O Interface

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I/O Timing: Transient Response

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Experimental Setup

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Performance results:

for the Tanner graph (TG) and T rellis (TR) decoders

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Measured results:

Showing performance as a function of supply voltage and speed for the Tanner graph decoder

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Measured results:

Showing performance as a function of supply voltage and speed for the Trellis graph decoder

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Energy Efficiency Figures:

Of Digital (top 2) and Analog Decoders (bottom 4)

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Comparison of Eb/N0 losses:

For the Tanner graph (TG) and T rellis (TR) decoders at different Vdd as a function of clock speed

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Summary

Overview of low power CMOS analog circuits f or iterative decoding A new topology for reducing supply voltage by at least 0.4 V Proposed topology used to implement two types of decoders The Trellis decoder achieved the lowest energy per bit of any reported iterative decoder

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