Introduction Paper presentation Ultra-Portable Devices Paper: - - PowerPoint PPT Presentation

Paper presentation – Ultra-Portable Devices

Paper:

• C. Winstead, C. Schlegel.

Analog Decoding: the State of the Art

Presented by:

ISSSTA 2004, Sydney, Australia, August 2004, pages 503- 511

Reza Meraji

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Introduction

• Viterbi algorithm by analog components (Add-compare-

select)

• Fully parallel analog soft iterative decoders (sum-product

algorithm) algorithm)

• A variety of decoders can be implemented in analog:

MAP, Turbo, LDPC, Block product Decoders

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Modern Iterative decoders

• Soft information component decoders (working based on

probabilities)

• Each component decoder computes extrinsic information

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• Decoder exchange this extrinsic information and decode

again (information sharing)

• Decoder’s calculation tends to improve after each iteration
• The simple ”sum” and ”product” operations are all that is

needed

Translinear circuits

• A translinear device: a device in which its current is an

exponential function of the voltage between two of its terminals

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• Bipolar transistors
• MOS devices biased in subthreshold

region

Translinear circuits

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Translinear circuits can be used for multiplication of currents

Basic Computational Elements

• Analog currents proportional to probabilities
• Translinear circuits for analog multiplications
• Shorting wires for summation

Sum and product operations are provided by translinear devices Log-domain processing? => work with voltages

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CMOS Analog Decoders

• MOS transistors in weak inversion or subthreshold region
• Current is typically less than 100 nA
• The transistor is never ”turned on” -> leakage in digital design

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• Consumed power in the transistor in the nano Watt range
• The transistor is slow => high throughput is obtained through

parallelism

CMOS Analog decoders

• Suitable for SOC design:

– Rejection of high frequency interferences – Produces no high-frequency interference

• Performance:
• Performance:

– Block length up to 256 coded bits – Throughput up to 500 Mbit/s (1 Mbit/s for low voltage/power)

• Extremely low energy operation

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Interfacing with a larger system

• Serial to parallel conversion (S/H circuits)
• Channel information expressed as a sequence of differential

voltages (LLRs)

• Parasitic effects

– Clock feed-through (or charge injections) – Substrate leakage

• Analog-Digital interface

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Analog Decoder Interface

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Some Challenging Issues

Simulations

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(8,4) Hamming decoder, simulated using importance sampling Importance sampling results for a (16,11)^2 analog product decoder

Some Challenging Issues

• Mismatch and larger decoders

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Performance loss due to mismatch for regular LDPC codes, based on Density Evolution

Summary

• Iterative algorithms for analog decoders
• Translinear circuits as decoder building blocks
• CMOS analog decoders
• Interface architecture
• Performance evaluation

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