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Outline Paper presentation Ultra-Portable Devices Introduction. Paper: Paper: VT-Sub-CMOS Logic. H Hendrawan S., Kaushik Roy, et al. d S K hik R t l Robust Subthreshold Logic for Ultra-Low Power Operation, Sub-DTMOS

SLIDE 1

Paper presentation – Ultra-Portable Devices

Paper: Paper:

H d S K hik R t l Hendrawan S., Kaushik Roy, et al. Robust Subthreshold Logic for Ultra-Low Power Operation, IEEE Transactions on Very large scale Integration (VLSI) Systems, VOL.9, NO.1, Date: February, 2001.

Presented by:

y,

S. M. Yasser Sherazi

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Outline

Introduction.
VT-Sub-CMOS Logic.
Sub-DTMOS Logic.
Results.
Summary.

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” Introduction ”

Power vs Frequency for various Vdd.

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’’VT-Sub-CMOS Logic’’

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SLIDE 2

”Stabalization Module”

LCM is the leakge sensor and control to SSB.
SSb applies appropriate bias to the substrate of transistor.

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”Leakage Current Monitor”

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’’Vcontrol Vs Vbb for various Temps.”

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”Self-substrate bias Circuit”

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SLIDE 3

’’Positive and Negative Pump Circuits’’

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”SUB-DTMOS LOGIC”

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’’Delay verses Vdd’’

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’’Power verses Vdd’’

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SLIDE 4

’’Power-delay Product versus Vdd’’

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’’VTC of sub-CMOS and sub-DT-CMOS Logic’’ Logic

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”Delay versus number of Fan-outs”

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”Sub-DT-Pseudo-NMOS Logic”

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SLIDE 5

”Delay versus Vdd”

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”Power versus Vdd”

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”Power-delay product versus Vdd”

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”VTC’s of sub-DT- and sub-Pseudo- NMOS logic” NMOS logic

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SLIDE 6

”On-current versus temp”

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”Delay versus temp”

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”PDP versus temperature”

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”Threshold voltage versus Vbs”

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SLIDE 7

”Delay versus Threshold Voltage”

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”PDP versus Threshold Voltage”

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”Effect of ∆Vth”

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” Effect of Temperature”

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SLIDE 8

”Conclusion”

Both VT-sub-CMOS and sub-DTMOS logic families show

i b t d t l t t t d superior robustness and tolerance to temperature and process variations than that of regularsubthreshold CMOS logic logic.

VT sub CMOS logic can be readily implemented in twin well
VT-sub-CMOS logic can be readily implemented in twin-well

process technology, but it requires additional circuitry for stabilization.

In contrast, sub-DTMOS logic does not require any additional

co as , sub OS og c does

equ e a y add o a

stabilization circuitry but can only be implemented in triple- well process technology.

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