Overview Background Deep submicron challenges Verification, - - PDF document

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Paper Review

DIVA - A reliable substrate for Deep Submicron Microarchitecture Design

• Todd Austin, Univ. of Michigan (1999)

ECE1718 MCA

• K.P. Tang

November 2008

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Overview

• Background

– Deep submicron challenges – Verification, testing, validation

• Motivation

– simply processor verification and lower test cost

• Diva Architecture

– Chkcomp, Chkcomm, Watchdog Timer

• How it works
• Diva observations
• Summary

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Deep submicron challenges

• Smaller geometry

– performance, power, cost

• Increasing complexity

– design, test, manufacturing

• Time to market, get it right the first time
• Costs

– NRE, design, test, manufacturing – opportunity cost (market share)

• Values

– Correctness, performance, cost, time

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Verification, testing, validation

• Verification

– Functionality and performance – Simulation and formal verification

• Testing

– Manufacturing

• Validation

– System integration – Did we build the right system?

• Verification needs to cover all programs, corner

cases

– Verification gap

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Verification gap

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Sources of errors

• Functional

– Logic (>60%)

• Timing

– Glitches, races, speed

• Manufacturing

– Defects

• Others

– Process, operating condition (temperature/voltage) variations – EM interference, radiation

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Design re-spins

Delays in re-spins = Lost time to market Many designs have

• ne or more re-spins

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DIVA checker

• DIVA

– Dynamic Implementation Verification Architecture

• Increase processor design reliability
• Separate microarchitectural processor design

and verification

• Detect and fix incorrect operation
• Become a run-time checker
• Lower verification costs and risks
• Improve time-to-market

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DIVA core and checker

IF – Intr. Fetch ID – Intr. Decode REN – Rename REG – Register EX – Execution MEM – Memory CT – Commit CHK – Check WT – Watchdog Timer Source: DIVA Source: DIVA -

• Todd Austin, Univ. of Michigan

Todd Austin, Univ. of Michigan

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DIVA checker

Source: DIVA - Todd Austin, Univ. of Michigan

• CHKcomp verifies results
• CHKcomm verifies register/memory inputs
• Watchdog timer detects lockups
• Simple, in-order scheduler, no reorder, low latency, accurate

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DIVA checker architecture

Source: DIVA - Todd Austin, Univ. of Michigan

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DIVA check mode

Source: DIVA - Todd Austin, Univ. of Michigan

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DIVA recovery mode

Source: DIVA - Todd Austin, Univ. of Michigan

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DIVA observations

Complex core processor

• Focus on fast, speculative, and

complex core design

• Branch predictions
• Cache prefetches

Checker processor

• Simple and low cost processor

core

• Take advantages of main core

branch predictions and cache prefetches

• Focus on fault detection and

correction (design errors, electrical faults, silicon defects, and even core failures)

• Checker must be high accuracy

and reliable

Source: DIVA - Todd Austin, Univ. of Michigan

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Beta release and launch

Source: DIVA - Todd Austin, Univ. of Michigan

Previous launch

time

Previous beta

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Self-tuned systems

Source: DIVA - Todd Austin, Univ. of Michigan

• Self tuning to maximize operating performance

– Built-in design margins from designers – Speed binning at manufacturing – Optimize operating frequency with voltage and temperature inputs

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DIVA checker verification

Source: DIVA - Todd Austin, Univ. of Michigan

• Simple checker processor core requires

complete functional verification

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DIVA checker core BIST

Source: DIVA - Todd Austin, Univ. of Michigan

Manufacturing defects

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If checker processor fail to check?

Source: DIVA - Todd Austin, Univ. of Michigan

Transient faults

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Replicate checker core

Source: DIVA - Todd Austin, Univ. of Michigan

Core redundancy

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Summary

Source: DIVA - Todd Austin, Univ. of Michigan

• Introduced DIVA core and DIVA checker
• DIVA can separate processor core design from

traditional costly and lengthy core verification

• DIVA pipelined checker core can be simple, fast (latency

insensitive), and low cost

• Core processor can tolerate permanent and transient

errors

• Beta release can help overlap processor launch with

verification

• Clock and voltage tuning system can optimize circuit
• perations
• DIVA must be reliable and functionally correct.

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Backup slides

Source: DIVA - Todd Austin, Univ. of Michigan

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Example operations

Source: DIVA - Todd Austin, Univ. of Michigan

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Register file and cache bandwidth

Source: DIVA - Todd Austin, Univ. of Michigan

R-4 extra register file ports, M-1 extra memory port 1 extra memory port is good enough

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Checker latency

Source: DIVA - Todd Austin, Univ. of Michigan

Minimal effect on core performance

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Exception rates

Source: DIVA - Todd Austin, Univ. of Michigan

One exception per x instruction Worst case performance