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ACCESS IC LAB
Graduate Institute of Electronics Engineering, NTU
ADSP ADSP-
- BF533 Peripherals
ACCESS IC LAB
Graduate Institute of Electronics Engineering, NTU
ADSP- -BF533 Peripherals BF533 Peripherals ADSP Advisor: Prof. - - PowerPoint PPT Presentation
ADSP- -BF533 Peripherals BF533 Peripherals ADSP Advisor: Prof. - - PowerPoint PPT Presentation
Graduate Institute of Electronics Engineering, NTU ADSP- -BF533 Peripherals BF533 Peripherals ADSP Advisor: Prof. Andy Wu 2004/10/14 ACCESS IC LAB ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Outline Outline
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Introduction Introduction
Peripheral -- The ADSP-BF533 (HS) processor contains a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance.
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Outline Outline
Introduction BF533 Peripherals[1] Using Peripherals
Lab: Blink
Reference
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ADSP ADSP-
- BF533 Peripherals[1]
BF533 Peripherals[1]
1. DMA Controllers 2. SPI 3. PPI/GPIO 4. SPORTS 5. UART 6. Timer/Counters
Real-Time Clock (RTC) Watchdog Timer Core Timer
7. Others
Debug/JTAG Interface Event Handler On-Chip PLL Capable of 1x To 63x Frequency Multiplication
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DMA -- Direct Memory Access DMA controllers features:
Multiple, independent, and automated data transfers.
DMA transfers occur between:
Internal memories and any of its DMA-capable peripherals. Any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller.
DMA-capable peripherals include:
PPI , SPORTs, SPI port, and UART.
Each individual DMA-capable peripheral has at least one dedicated DMA channel.
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DMA controller supports:
1-dimensional (1D) DMA transfers. 2-dimensional (2D) DMA transfers.
DMA transfer initialization can be implemented from:
Registers Sets of parameters called descriptor blocks.
There are two memory DMA channels:
Provided for transfers between the various memories, including external SDRAM, ROM, SRAM, and flash memory.
Memory DMA transfers can be controlled by:
Descriptor-based methodology (flexible). Register-based auto-buffer mechanism (standard).
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Examples of DMA types supported by the DMA controller include:
A single, linear buffer that stops upon completion. A circular, auto-refreshing buffer that interrupts on each full
- r fractionally full buffer.
1-D or 2-D DMA using a linked list of descriptors. 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page.
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SPI -- Serial Peripheral Interface Full-duplex, synchronous serial interface
Three pins for transferring data:
two data pins
Master Output-Slave Input (MOSI) Master Input-Slave Output (MISO)
clock pin
Serial Clock (SCK)
SPI chip select input pin (SPISS):
lets other SPI devices select the processor.
DMA controller
Unidirectional
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PPI -- Parallel Peripheral Interface Can connect directly to:
Parallel A/D and D/A converters ITU-R 601/656 video encoders and decoders Other general-purpose peripherals.
Dedicated input clock pin
Up to 3 frame synchronization pins Up to 16 data pins. The input clock supports parallel data rates up to half the system clock rate.
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SPORTS -- Serial ports Two dual-channel synchronous serial ports
SPORT0 and SPORT1 Serial and multiprocessor communications
The SPORTs support the following features:
I2S capable operation. Bidirectional operation Each SPORT has two sets of independent transmit and receive pins, enabling eight channels of I2S stereo audio. More
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UART -- Universal Asynchronous Receiver/Transmitter Support
full-duplex asynchronous transfers of serial data
DMA-supported
two dedicated DMA channels, one for transmit and one for receive lower default priority than most DMA channels
low service rates
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Timer*3 Real-Time Clock Watchdog Timer Core Timer
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Event Handler Debug/JTAG Interface On-Chip PLL Capable of 1x To 63x Frequency Multiplication
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Outline Outline
Introduction BF533 Peripherals[1] Using Peripherals
Lab: Blink
Reference
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Using Peripherals Using Peripherals
./Analog Devices/VisualDSP 3.5 16-Bit/EZ- Kits/ADSP-BF533/Examples readme.txt
Ex: #include<defBF533.h>, startup.asm
Help Index
Ex: EVTx, RTS, lsetup()
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LAB: Blink LAB: Blink
Goal
Access LED Learn about I/O, interrupts, and timer
Files
main.c Initialisation.c ISRs.c BF533 Flags.h readme.txt
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Initialisation.c Initialisation.c
Init_Flags()
switch connected to PF8 (SW4)
Init_Timers()
Timer0 for PWM mode
Init_EBIU()
EBIU setup (External Bus Interface Unit)
Init_Flash()
sets the pin direction of Port B in Flash A
Init_Interrupts()
Interrupt configuration
Help ^_^ Ex: FIO_INEN TIMERx_CONFIG EBIU_AMBCTL SIC_IARx register_handler( ) Flash General-Purpose IO
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ISRs.c ISRs.c
EX_INTERRUPT_HANDLER(Timer0_ISR)
timer interrupt LED ( !)
EX_INTERRUPT_HANDLER(FlagA_ISR)
SW4 FIO clear (SW !) LED (
- r
!)
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Turn on switch SW9_1 [2](p1-6, p3-10) Build & Run Push button SW4 and see the change
Example: SW4 SW5 (SW9 !)
void Init_Flags(void) { *pFIO_INEN = 0x0200; *pFIO_DIR = 0x0000; *pFIO_EDGE = 0x0200; *pFIO_MASKA_D = 0x0200; } EX_INTERRUPT_HANDLER(FlagA_ISR) { *pFIO_FLAG_C = 0x0200; }
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SW4 SW7 LED
time, direction, others Blink
I/O, interrupt, timer
Any other things
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Outline Outline
Introduction BF533 Peripherals[1] Using Peripherals
Lab: Blink
Reference
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