Modeling the Overshooting Effect for CMOS Inverter in Nanometer - - PowerPoint PPT Presentation
Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies Zhangcai Huang , Hong Yu , Atsushi Kurokawa and Yasuaki Inoue Graduate School of Information, Production and Systems, Waseda University, Kitakyushu,
1
2
3
Ip In ICL PMOS NMOS CM ICM Vin Vout
The differential equation for the CMOS inverter The input voltage for the falling input ramp is expressed as
Principles of CMOS VLSI Design: A Systems Perspective
“CM is known as the Miller effect, but is seldom of importance in digital
5
in D
50 −
in r
D
For traditional process technologies, the effect of overshooting is very small and can be neglected
6
tr and td decrease much faster than tov with the increasing of gate sizes. And tov is equal to or larger than tr. With the scaling of technology process, tov becomes much important for delay time.
7
Short-circuit power consumption The overshooting time is one important parameter for power consumption estimation.
8
tov=0. tov = (Vt/Vdd)tin
The overshooting time is neglected
empirical expressions
analytical model for the evaluation of power consumption …”, TCAD 2002.
The overshooting time is assumed as simple value
9
Ip In ICL PMOS NMOS CM ICM
20 40 60 80 100 120 −100 −50 50 100 150 200 250 300
Q1 Q2 tvmin tov IL(tov)
Times (ps) Current (uA) Charging period Discharging period
PMOS NMOS Vin Vout ICM Ip In ICL CL
( )
ˆ
1 ˆ
n G S T H N L M
V V M C C
n G S T H N
d V in C d t V t e V V
β
β
− − +
⎡ ⎤ ⎢ ⎥ = − ⎢ ⎥ − ⎣ ⎦
12
20 40 60 80 100 120 −100 −50 50 100 150 200 250 300
Q1 Q2 tvmin tov IL(tov)
Times (ps) Current (uA) Charging period Discharging period 20 40 60 80 100 120 −100 100 200 300 400 500 600 700
In Ip tp tov tvmin
Times (ps)
Current (uA)
13
The overshooting time has minimum values. Minimum delay > Minimum overshooting time
in r
D
t t t t 2 1 − + =
14
15
The sensitivities of the overshooting time with respect to the variation sources. With respect to the variation of length. With respect to the variation of threshold voltage. In recent technologies, the variability of circuit performance due to the process variation has become a significant concern. As process geometries continue to shrink, the evaluation for critical device parameters is becoming more and more difficult due to the significant variations
16
in r
D
t t t t 2 1 − + =
Variation of L has no influence on the
Statistical Timing Analysis” ICCAD-2005
Variation of L has significant influence on the gate delay. Variation of L has the influence only on the rising time.
17
1. With input time decreases, the influence due to the Tox decreases greatly. 2. The influence due to L is 0. 3. With the scaling of process technologies, the variation of Vt increases, the influence due to Vt will increase greatly. International Technology Roadmap for Semiconductors (ITRS) 2005.
18
19
J.L. Rossell: “Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers”, TCAD 2002.
20
J.L. Rossell: “Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers”, TCAD 2002.
21
22
rising time, but has almost no influence on overshooting time. has almost no influence on overshooting time.
Vt has the most significant influence on has the most significant influence on
23