LIU-ABT systems: PSB BI.DIS10 controls Agenda: - - PowerPoint PPT Presentation

liu abt systems psb bi dis10 controls
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LIU-ABT systems: PSB BI.DIS10 controls Agenda: - - PowerPoint PPT Presentation

CERN TE-ABT-EC LIU-ABT systems: PSB BI.DIS10 controls Agenda: https://indico.cern.ch/event/493116/ Timing system (Christophe Chanavat) Fast interlocks studies (Felipe Cordobes Dominguez) IGBTs R&D program (Tobias


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SLIDE 1

LIU-ABT systems: PSB BI.DIS10 controls

  • Agenda: https://indico.cern.ch/event/493116/
  • Timing system (Christophe Chanavat)
  • Fast interlocks studies (Felipe Cordobes Dominguez)
  • IGBT’s R&D program (Tobias Stadlbauer & co)
  • General controls (Roger Andrew Barlow)

prepared by R.A.Barlow

1

CERN

TE-ABT-EC

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SLIDE 2

2

BI.DIS10

Generator prototype, Jura 6 Controls:

  • JURA 6 SLOW CONTROL sufficiently

advanced for system to pulse.

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SLIDE 3

3

BI.DIS10

Generator prototype, Jura 6 Controls:

  • PFN temps and IGBT powering
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SLIDE 4

4

BI.DIS10

Generator prototype, Jura 6 Controls:

  • PFN fan controls
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SLIDE 5

5

BI.DIS10

Generator prototype, Jura 6 Controls:

  • TECHNIX integrated
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SLIDE 6

6

BI.DIS10

Generator prototype, Jura 6 Controls:

  • WinCC trend of fan speed and

temperatures

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SLIDE 7

7

BI.DIS10

Generator prototype, Jura 6 Controls, to do:

  • Jitter, optical links, new ideas
  • IGBT drivers PS protection

Software:

  • Interlock validation, OV, OI, S/C for power

supplies

  • RESET issue with TECHNIX

Next Step:

  • Front cell adjustments
  • Close PFN
  • Reliability runs and thermal studies
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SLIDE 8

BCER.306 BCER.306 BCER.305 BCER.304 BCER.303 BCER.302 BCER.301 BCER.300 BCER.329 BCER.328 PFN.4 BCER.323 PFN.0 BCER.324 PFN.spare BCER.338 PFN.1 BCER.339 PFN.3 BCER.443 PFN.2 BCER.444 BCER.436 BCER.435

PDC system Master Controls Timing & Acquisitions GEN1 GEN2 GEN3 GEN4 GEN5 GENspare Dummy Load Patch panels

Magnet

8

BI.DIS10 generator change tactics

EC strategy

  • Feedthrough patch
  • HV cable Bundle detection
  • More flexibility…but
  • More complex cabling
  • DIC changes
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SLIDE 9

9

BI.DIS10

New rack layout

5 10 15 20 25 30 35 40 45

BCER.305 BCER.304 BCER.303 BCER.302 BCER.301 BCER.306

Reglette unit Reglette unit Optical trigger chassis AFO systems (type 1 & 2) VME front_end

BCER.300 BCER.329 PDC unit BCER.328

AUL system SCOPE

OASIS

CIBUS – BIS system Timing

Timing IPOC PPU signals Timing

Reglette unit Reglette unit Reglette unit AUL system

EDS controller AUL

Master CPU/ HV cable presence Optical trigger chassis AFO systems (type 1 & 2) VME front_end AUL system

EDS controller AUL

Reglette unit

GEN6 GEN5 GEN4 GEN3 GEN2 GEN1

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SLIDE 10

BI.DIS10

Documentation

  • Engineering Specification, BI.DIS10 CONTROLS, First review by EC, lot’s of

changes, feedback from FCD and BM also, still evolving !