liu abt systems psb bi dis10 controls
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LIU-ABT systems: PSB BI.DIS10 controls Agenda: - PowerPoint PPT Presentation

CERN TE-ABT-EC LIU-ABT systems: PSB BI.DIS10 controls Agenda: https://indico.cern.ch/event/493116/ Timing system (Christophe Chanavat) Fast interlocks studies (Felipe Cordobes Dominguez) IGBTs R&D program (Tobias


  1. CERN TE-ABT-EC LIU-ABT systems: PSB BI.DIS10 controls • Agenda: https://indico.cern.ch/event/493116/ • Timing system (Christophe Chanavat) • Fast interlocks studies (Felipe Cordobes Dominguez) • IGBT’s R&D program (Tobias Stadlbauer & co) • General controls (Roger Andrew Barlow) prepared by R.A.Barlow 1

  2. BI.DIS10 Generator prototype, Jura 6 Controls:  JURA 6 SLOW CONTROL sufficiently advanced for system to pulse. 2

  3. BI.DIS10 Generator prototype, Jura 6 Controls:  PFN temps and IGBT powering 3

  4. BI.DIS10 Generator prototype, Jura 6 Controls:  PFN fan controls 4

  5. BI.DIS10 Generator prototype, Jura 6 Controls:  TECHNIX integrated 5

  6. BI.DIS10 Generator prototype, Jura 6 Controls:  WinCC trend of fan speed and temperatures 6

  7. BI.DIS10 Generator prototype, Jura 6 Controls, to do: • Jitter, optical links, new ideas • IGBT drivers PS protection Software: • Interlock validation, OV, OI, S/C for power supplies • RESET issue with TECHNIX Next Step: • Front cell adjustments • Close PFN • Reliability runs and thermal studies 7

  8. • • • • • BCER.306 BCER.306 GENspare DIC changes More complex cabling More flexibility…but HV cable Bundle detection Feedthrough patch GEN5 BCER.305 GEN4 BCER.304 GEN3 BCER.303 GEN2 BCER.302 BI.DIS10 generator change tactics BCER.301 GEN1 Timing & Acquisitions BCER.300 PDC system BCER.329 Master Controls BCER.328 EC strategy PFN.3 PFN.spare PFN.4 BCER.443 BCER.338 BCER.323 PFN.2 PFN.1 PFN.0 BCER.444 BCER.339 BCER.324 Dummy Load BCER.436 Patch panels BCER.435 Magnet 8

  9. BI.DIS10 New rack layout BCER.306 BCER.305 BCER.304 BCER.303 BCER.302 BCER.301 BCER.300 BCER.329 BCER.328 45 Timing AUL system AUL system AUL system 40 Optical trigger chassis Optical trigger chassis 35 Timing AFO systems (type 1 & 2) AFO systems (type 1 & 2) 30 VME front_end VME front_end SCOPE 25 Master CPU/ HV cable presence PDC unit IPOC 20 OASIS 15 EDS controller EDS controller PPU signals 10 CIBUS – BIS system AUL AUL Timing 5 Reglette unit Reglette unit Reglette unit Reglette unit Reglette unit Reglette unit 0 GEN1 GEN2 GEN3 GEN4 GEN5 GEN6 9

  10. BI.DIS10 Documentation  Engineering Specification, BI.DIS10 CONTROLS, First review by EC, lot’s of changes, feedback from FCD and BM also, still evolving !

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