III-V Channel Transistors Jess A. del Alamo Professor Microsystems - - PowerPoint PPT Presentation

III-V Channel Transistors

Jesús A. del Alamo Professor Microsystems Technology Laboratories MIT

24 April 2017 Acknowledgements:

• Students and collaborators: D. Antoniadis, J. Lin, W. Lu, A. Vardi, X. Zhao
• Sponsors: Applied Materials, DTRA, KIST, Lam Research, Northrop Grumman,

NSF, Samsung

• Labs at MIT: MTL, EBL

Moore’s Law at 50: the end in sight?

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Moore’s Law

Moore’s Law = exponential increase in transistor density

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Intel microprocessors

2016: Intel 22-core Xeon Broadwell-E5 7.2B transistors

Moore’s Law

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?

How far can Si support Moore’s Law?

Transistor scaling  Voltage scaling  Performance suffers

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Transistor current density:

Goals:

• Reduced footprint with moderate short-channel effects
• High performance at low voltage

Intel microprocessors Intel microprocessors

Supply voltage:

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Moore’s Law: it’s all about MOSFET scaling

• 1. New device structures with improved scalability:
• 2. New materials with improved transport characteristics:

n-channel: Si  Strained Si  SiGe  InGaAs p-channel: Si  Strained Si  SiGe  Ge  InGaSb

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III-V electronics in your pocket!

Contents

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• 1. Self-aligned Planar InGaAs MOSFETs

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Lin, IEDM 2012, 2013, 2014 W Mo Lee, EDL 2014; Huang, IEDM 2014 selective MOCVD Sun, IEDM 2013, 2014 Chang, IEDM 2013 reacted NiInAs dry-etched recess implanted Si + selective epi

Self-aligned Planar InGaAs MOSFETs @ MIT

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Lin, IEDM 2012, 2013, 2014

Recess-gate process:

• CMOS-compatible
• Refractory ohmic contacts
• Extensive use of RIE

W Mo

0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.2 0.4 0.6 0.8 1.0

Lg=20 nm Ron=224 m 0.4 V

Id (mA/m) Vds (V)

Vgs-Vt= 0.5 V

• Ohmic contact first, gate last
• Precise control of vertical (~1 nm), lateral (~5 nm) dimensions
• MOS interface exposed late in process

Fabrication process

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W/Mo n+ InGaAs/InP InGaAs/InAs InAlAs SiO2 InP -Si Resist Mo Pad HfO2

Mo/W ohmic contact + SiO2 hardmask SF6, CF4 anisotropic RIE CF4:O2 isotropic RIE Cl2:N2 anisotropic RIE Digital etch

Waldron, IEDM 2007

Finished device

Lin, EDL 2014

O2 plasma H2SO4

• Channel: In0.7Ga0.3As/InAs/In0.7Ga0.3As (tch=9 nm)
• Gate oxide: HfO2 (2.5 nm, EOT~ 0.5 nm)

Highest performance InGaAs MOSFET

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Lg=70 nm:

• Record gm,max = 3.45 mS/µm at Vds= 0.5 V
• Ron = 190 Ω.µm

Lin, EDL 2016

3.45 mS/m

Exceeds best HEMT!

Excess OFF-state current

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OFF-state current enhanced with Vds  Band-to-Band Tunneling (BTBT) or Gate-Induced Drain Leakage (GIDL)

Lin, IEDM 2013

• 0.6 -0.4 -0.2 0.0

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• 11

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• 9

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• 7

10

• 5

Lg=500 nm Vds=0.3~0.7 V step=50 mV

Id(A/m) Vgs (V)

Transistor fails to turn off:

Vds ↑

• 0.4 -0.2 0.0 0.2

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• 11

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• 9

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• 7

10

• 5

W/ BTBT+BJT W/O BTBT Vds=0.3~0.7 V step=50 mV

Id (A/m) Vgs (V)

Excess OFF-state current

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Lg↓  OFF-state current ↑  bipolar gain effect due to floating body

Lin, EDL 2014

• 0.6 -0.4 -0.2 0.0

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• 11

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• 9

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• 7

10

• 5

Lg=500 nm Vds=0.3~0.7 V step=50 mV

Id(A/m) Vgs (V)

• 0.6 -0.4 -0.2 0.0

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• 8

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• 7

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• 5

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500 nm 280 nm 120 nm T=200 K Vds=0.7 V

Id (A/m) Vgs-Vt (V)

Lg=80 nm

Vds ↑

Simulations

w/ BTBT+BJT w/o BTBT+BJT

Lg=500 nm

Lin, TED 2015

• 2. InGaAs FinFETs

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Intel Si Trigate MOSFETs

Bottom-up InGaAs FinFETs

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Si

Waldron, VLSI Tech 2014 Aspect-Ratio Trapping Fiorenza, ECST 2010 Epi-grown fin inside trench

Top-down InGaAs FinFETs

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Kim, IEDM 2013

60 nm

dry-etched fins Radosavljevic, IEDM 2010

20 40 60 0.0 0.5 1.0 1.5 2.0

1.8 1 0.8 0.57

InGaAs FinFETs

5.3 4.3

Si FinFETs

gm[mS/m] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

FinFET benchmarking

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gm normalized by width of gate periphery

• State-of-the-art Si FinFETs: Wf=7 nm

Natarajan, IEDM 2014

channel aspect ratio

20 40 60 0.0 0.5 1.0 1.5 2.0

1.8 1 0.8 0.57

InGaAs FinFETs

5.3 4.3

Si FinFETs

gm[mS/m] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

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Thathachary, VLSI 2015

gm normalized by width of gate periphery

• Narrowest InGaAs FinFET fin: Wf=15 nm
• Best channel aspect ratio of InGaAs FinFET: 1.8
• gm much lower than planar InGaAs MOSFETs

Oxland, EDL 2016 Radosavljevic, IEDM 2011 Kim, IEDM 2013 Natarajan, IEDM 2014

channel aspect ratio

FinFET benchmarking

InGaAs FinFETs @ MIT

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Vardi, DRC 2014, EDL 2015, IEDM 2015

Key enabling technologies: BCl3/SiCl4/Ar RIE + digital etch

• Sub-10 nm fin width
• Aspect ratio > 20
• Vertical sidewalls

InGaAs FinFETs @ MIT

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Vardi, VLSI Tech 2016 Vardi, EDL 2016

• CMOS compatible process
• Mo contact-first process
• Fin etch mask left in place  double-gate MOSFET

InAlAs InGaAs

n+‐InGaAs

W/Mo Lg SiO2 HSQ High‐K InP δ ‐ Si InP Mo Mo HSQ High‐K InGaAs

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Most aggressively scaled FinFET

Wf=7 nm, Lg=30 nm, Hc=40 nm (AR=5.7), EOT=0.6 nm: Vardi, EDL 2016 At VDS=0.5 V:

• gm=900 µS/µm
• Ron=320 Ω.µm
• Ssat=100 mV/dec
• 0.4
• 0.2

0.0 0.2 0.4 200 400 600 800 1000 VDS=0.5 V

gm max=900 S/m

gm [S/m] VGS [V]

• 0.5 -0.4 -0.3 -0.2 -0.1 0.0

0.1 0.2 0.3 0.4 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3

VDS=50 mV DIBL=90 mV/V

Id [A/m] VGS [V]

Ssat=100 mV/dev VDS=500 mV

0.0 0.1 0.2 0.3 0.4 0.5 100 200 300 400 500 Id [A/m]

VDS [V] VGS=-0.5 to 0.75 VGS=0.25 V

Current normalized by 2xHc

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100 200 300 400 500 600 700

• 0.6
• 0.4
• 0.2

0.0 0.2 0.4

EOT

VT [V] Lg [nm] 100 200 300 400 500 600 700 50 100 150 200 250 A: Al2O3, EOT=2.8 nm B:Al2O3/HfO2, EOT=1 nm C: HfO2, EOT=0.6 nm Ssat [mV/dec] Lg [nm]

EOT

60 mV/dec 100 200 300 400 500 600 700 200 400 600 800 1000 1200 1400 1600

EOT

VDS=0.5 V Wf20-22 nm

gm [S/m] Lg [nm] 100 200 300 400 500 600 700 50 100 150 200 250 300 350

EOT

Ioff=100 nA/m VDS=0.5 V Ion [A/m] Lg [nm]

Classical scaling with Lg and EOT

Lg and EOT scaling

100 1000 50 100 150

Wf=7 nm Wf=12 nm Wf=17 nm Wf=22 nm

Ssat,min [mV/dec] Lg [nm] 60 mV/dec

Fin width scaling (EOT=0.6 nm)

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• Non-ideal fin width scaling
• High Dit (~5x1012 cm-2.eV-1); mobility degradation; line edge roughness

Contaminated by gate leakage

100 200 300 500 1000 1500 2000 2500 12 17 Wf=22 nm Ron [m] Lg [nm] 7 nm 50 100 150 200 250 300

• 0.3
• 0.2
• 0.1

0.0 0.1 0.2 0.3

 Wf=22 nm Wf= 5 nm

VT [V] Lg [nm] 100 200 300 400 500 600 200 400 600 800 1000 1200 1400 1600  Wf= 5 nm gm max [S/m] Lg [nm] Wf=22nm

InGaAs FinFETs: gm benchmarking

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gm normalized by width of gate periphery:

• First InGaAs FinFETs with Wf<10 nm
• Record results for InGaAs FinFETs with Wf < 25 nm
• Still short of Si FinFETs (though they operate at VDD=0.8 V)

Hc Wf Hc

Double gate Trigate

20 40 60 0.0 0.5 1.0 1.5 2.0

1.8 1 0.8 0.57 5.7 3.3 2.31.8

InGaAs FinFETs

5.3 4.3

Si FinFETs

gm[mS/m] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

InGaAs FinFETs: gm benchmarking

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gm normalized by fin width (FOM for density): Doubled gm/Wf over earlier InGaAs FinFETs

Vardi, EDL 2016

Hc Wf Wf Hc

20 40 60 5 10 15 20

1 1.8 0.57 0.8 5.7 3.3 2.31.8

InGaAs FinFETs

5.3 4.3

Si FinFETs (VDD=0.8 V)

gm/Wf [mS/m] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

Impact of fin width on VT

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• Strong VT sensitivity for Wf < 10 nm; much worse than Si
• Due to quantum effects
• Big concern for future manufacturing

InGaAs doped-channel FinFETs: 50 nm thick, ND~1018 cm-3

Vardi, IEDM 2015

T=90K

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• 3. Vertical nanowire MOSFET:

ultimate scalable transistor

Vertical NW MOSFET:  uncouples footprint scaling from Lg, Lspacer, and Lc scaling Lc Lg Lspacer

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Vertical nanowire MOSFET for 5 nm node

Yakimets, TED 2015 Bao, ESSDERC 2014

Vertical NW:  power, performance and area gains w.r.t. Lateral NW or FinFET

5 nm node 30% area reduction in 6T‐SRAM 19% area reduction in 32 bit multiplier

InGaAs Vertical Nanowires on Si by direct growth

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Björk, JCG 2012 Selective-Area Epitaxy Au seed Vapor-Solid-Liquid (VLS) Technique InAs NWs on Si by SAE Riel, MRS Bull 2014

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InGaAs VNW MOSFETs by top-down approach @ MIT

• Sub-20 nm NW diameter
• Aspect ratio > 10
• Smooth sidewalls

Zhao, EDL 2014 Key enabling technologies:

• RIE = BCl3/SiCl4/Ar chemistry
• Digital Etch (DE) =

O2 plasma oxidation H2SO4 oxide removal

15 nm 240 nm

InGaAs VNW Mechanical Stability for D<10 nm

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8 nm InGaAs VNWs: Yield = 0%

Broken NW

Difficult to reach 10 nm VNW diameter due to breakage

InGaAs VNW Mechanical Stability for D<10 nm

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8 nm InGaAs VNWs: Yield = 0%

Broken NW

Difficult to reach 10 nm VNW diameter due to breakage Water-based acid is problem:

Surface tension (mN/m):

• Water: 72
• Methanol: 22
• IPA: 23

Solution: alcohol-based digital etch

Alcohol-Based Digital Etch

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10% HCl in IPA Yield = 97% 10% HCl in DI water Yield = 0%

Alcohol-based DE enables D < 10 nm

Broken NW

Radial etch rate: 1.0 nm/cycle Radial etch rate: 1.0 nm/cycle

8 nm InGaAs VNWs Lu, EDL 2017

InGaAs Digital Etch

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First demonstration of D=5 nm diameter InGaAs VNW (Aspect Ratio > 40) Lu, EDL 2017

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InGaAs VNW-MOSFETs by top-down approach @ MIT

Top-down approach: flexible and manufacturable

n+ InGaAs, 70 nm i InGaAs, 80 nm n+ InGaAs, 300 nm

Starting heterostructure: n+: 6×1019 cm‐3 Si doping

Process flow

Tomioka, Nature 2012 Persson, DRC 2012 Zhao, IEDM 2013

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NW-MOSFET I-V characteristics: D=40 nm

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Single nanowire MOSFET:

• Lch= 80 nm
• 3 nm Al2O3 (EOT = 1.5 nm)
• gm,pk=720 μS/μm @ VDS=0.5 V
• Slin=70 mV/dec, Ssat=80 mV/dec
• DIBL=88 mV/V
• 0.2

0.0 0.2 0.4 0.6 10

• 10

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• 9

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• 8

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Vds=0.5 V

Vgs(V) Is (A/m)

Vds=0.05 V

0.0 0.1 0.2 0.3 0.4 0.5 50 100 150 200 250 300

Vgs=-0.2 V to 0.7 V in 0.1 V step

Vds (V)

Is A/m)

• 0.2

0.0 0.2 0.4 0.6 100 200 300 400 500 600 700 800 Vgs(V) gm (S/m) Vd= 0.5 V

gm,pk=720 μS/μm

Slin = 70 mV/dec Ssat = 80 mV/dec DIBL = 88 mV/V

Zhao, CSW 2017

200 400 600 200 400 600 800 1000 1200 1400 Vds=0.5 V

Ssat (mV/dec)

gm,pk (S/m)

Tanaka, APEX 2010

Tomioka, IEDM 2011

Tomioka, Nature 2012 Persson, DRC 2012 Persson, EDL 2010

Zhao, IEDM 2013

Berg, IEDM 2015 This work

Top‐down VNW‐MOSFETs as good as bottom up devices

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Persson, DRC 2012 Tomioka, Nature 2012 Tanaka, APEX 2010 Berg, IEDM 2015

InGaAs VNW-MOSFETs Benchmark

This work

How are we doing in terms of short-channel effects?

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del Alamo, J-EDS 2016 Slin: linear subthreshold swing Lg= gate length λc= electrostatic scaling length: f(tox, tch) Ideal scaling

FinFET Planar-MOSFET VNW MOSFET

• Reasonable scaling behavior but…
• Excessive Dit

• 4. InGaSb p–type MOSFETs

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Nainani, IEDM 2010

Planar InGaSb MOSFET demonstrations:

Takei, Nano Lett. 2012

InGaSb p–type FinFETs @ MIT

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Lu, IEDM 2015

Key enabling technology:

• BCl3/N2 RIE
• [digital etch under development]

15 nm fins, AR>13 20 nm fins, 20 nm spacing

• Smallest Wf = 15 nm
• Aspect ratio >10
• Fin angle > 85°
• Dense fin patterns

Si-compatible contacts to p+-InAs

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Lu, IEDM 2015

Ni/Ti/Pt/Al on p+-InAs (circular TLMs): Record ρc: 3.5x10-8 Ω.cm2 at 400oC

InGaSb p-type FinFETs

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Lu, IEDM 2015

• Fin etch mask left in place  double-gate MOSFET
• Channel: 10 nm In0.27Ga0.73Sb (compressively strained)
• Gate oxide: 4 nm Al2O3 (EOT=1.8 nm)

• First InGaSb FinFET
• Peak gm approaches best InGaSb planar MOSFETs
• Poor turn off

InGaSb FinFET I-V characteristics

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• Lg = 100 nm, Wf = 30 nm (AR=0.33)
• Normalized by conducting gate periphery

Lu, IEDM 2015

0.01 0.1 1 10 100 10 100

Yuan, 2013 [7] Nainani, 2010 [8] Chu, 2014 [11] Xu, 2011 [12] Nagaiah, 2011 [13]

In0.36Ga0.64Sb GaSb

gm (S/m) Lg (m)

This work (FinFET) In0.27Ga0.73Sb GaSb In0.35Ga0.65Sb In0.2Ga0.8Sb

Planar MOSFETs

InGaSb p-Channel FinFETs (2nd gen.)

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Vd(V)

• 1
• 0.8
• 0.6
• 0.4
• 0.2

50 100 150 200

Vg: 1 to -1.6 in -0.4V step, Rtot:2.30e+03

• m
• Lg = 100 nm, Wf = 18 nm (AR=0.42)
• Channel: 7.5 nm In0.4Ga0.6Sb
• gm,max = 200 µS/µm
• Still poor turn-off  need digital etch, better sidewall passivation

0.01 0.1 1 10 100 10 100

Gen 2 In0.4Ga0.6Sb Gen 1 In0.2Ga0.8Sb Yuan, 2013 Nainani, 2010 Chu, 2014 Xu, 2011 Nagaiah, 2011

In0.36Ga0.64Sb GaSb

gm (S/m) Lg (m)

Gen 1 In0.27Ga0.73Sb

GaSb In0.35Ga0.65Sb In0.2Ga0.8Sb

Planar MOSFETs

Lu, CSW 2017

• 5. Co-integration of SiGe p-MOSFETs

and InGaAs MOSFETs on SOI

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InGaAs n-MOSFET

Czornomaz, VLSI Tech 2016

SiGe p-MOSFET 6T-SRAM

SiGe InGaAs Si SiO2

Confined Epitaxial Lateral Overgrowth

Conclusions

1. Great recent progress on planar, fin and nanowire InGaAs MOSFETs 2. Device performance still lacking for multigate designs 3. P-type InGaSb MOSFETs in their infancy 4. Many, MANY issues to work out:

sub-10 nm fin/nanowire fabrication, self-aligned contacts, device asymmetry, introduction of mechanical stress, VT control, sidewall roughness, device variability, BTBT and parasitic HBT gain, trapping, self- heating, reliability, NW survivability, co-integration on n- and p-channel devices on Si, …

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Hype curve for III-V CMOS?

# Papers on III-V CMOS at IEDM Year

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A lot of work ahead but… exciting future for III-V electronics