Encountering Gate Oxide Breakdown Encountering Gate Oxide Breakdown - - PowerPoint PPT Presentation

Encountering Encountering Gate Oxide Breakdown Gate Oxide Breakdown with with Shadow Transistors Shadow Transistors to to Increase Reliability Increase Reliability Shadow Transistors Shadow Transistors to to Increase Reliability Increase Reliability

Claas Cornelius1, Frank Sill2, Hagen Sämrow1, Jakob Salzmann1, Dirk Timmermann1, Diógenes Cecílio da Silva Jr.2 , g

1University of Rostock, Germany 2 Federal University of Minas Gerais (UFMG), Brazil

Gramado, 3rd September 2008 1

Focus / Main ideas Focus / Main ideas

1 Reliability regarding oxide breakdown

• 1. Reliability regarding oxide breakdown

2 Transistor / Gate level approach

• 2. Transistor / Gate level approach
• 3. Selective insertion / thick oxide devices

2

Cornelius et. al: Shadow Transistors

Outline Outline

Motivation

T h l d l t – Technology development – Error classification Ti D d t Di l t i B kd (TDDB) – Time-Dependent Dielectric Breakdown (TDDB)

Shadow Transistors

U d d l – Used model – Main Ideas Al ith – Algorithm

Results Conclusion

3

Cornelius et. al: Shadow Transistors

Motivation Motivation

130 nm

150 nm

500

Technology development

Wolfdale 410 Mill.

130 nm 90 nm

100 nm

300 400

• logy

s [Mill.]

65 nm 45 nm

50 nm

200 300

Techno ansistors

Northwood Prescott 125 Mill.

0 nm

100

Tra

Northwood 55 Mill. Yonah, 151 Mill.

2002 2004 2006 2008

Year

Probability for failures increases due to: Probability for failures increases due to: Increasing transistor count Shrinking technology

4

Cornelius et. al: Shadow Transistors

Motivation Motivation

Error classification

Error Permanent Temporary

Soft errors, Voltage drop, Coupling, …

Reduced Performance Malfunction

Process variations, Electro- migration, Oxide wearout ... Electromigration, Oxide breakdown ... Oxide wearout Oxide breakdown 5

Cornelius et. al: Shadow Transistors

Motivation Motivation

Time-Dependent Dielectric Breakdown (TDDB)

• Tunneling currents

g Wear out of gate oxide

• Creation of conducting path

g p between Gate and Substrate, Drain, Source

• Depending on electrical field over

gate oxide, temperature (exp.), ( )

Source: Pey&Tung

and gate oxide thickness (exp.)

• Also: abrupt damage due to

t lt ( El t extreme overvoltage (e.g. Electro- Static Discharge) 6

Cornelius et. al: Shadow Transistors

Source: Pey&Tung

Motivation Motivation

TDDB ─ Trends

Increasing probability for Gate-Oxide-Breakdown

10000

• x

16

pe β)

100 1000

t Density Jo

8 12

Weibull slop

high-k? 1 10

Current

4

eliability (W

1 180 nm 90 nm 45 nm 22 nm

Technology

2 4 6 8 10 12

Re Gate Oxide Thickness [nm]

Source: Borkar, Intel Source: Kauerauf, EDL, 2002

7

Cornelius et. al: Shadow Transistors

Shadow Transistors Shadow Transistors

TDDB between gate and channel

Applied model

Gate

TDDB between gate and channel

For an Inverter, 65nm-BPTM: Gate Oxide

Drain Source

15 20 75% 100%

,

10 15 50% 75%

Vout/VDD

• rel. delay

Model:

5 0% 25%

RGC

Model:

‐RGC [kΩ] →

W1 W2

Based on: Segura et. al., “A Detailed Analysis of GOS Defects i MOS T i t T ti I li ti t Ci it L l” 1995

W= W1+W2

8

Cornelius et. al: Shadow Transistors

in MOS Transistors: Testing Implications at Circuit Level” 1995.

Shadow Transistors Shadow Transistors

TDDB between gate and source/drain

Applied model

TDDB between gate and source/drain

For an Inverter, 65nm-BPTM:

Gate

100%

,

V /V

Gate Oxide

Drain Source

50% 75%

Model: Vout/VDD

0% 25%

Model:

0% ‐RGC [kΩ] →

Based on: Segura et. al., “A Detailed Analysis of GOS Defects i MOS T i t T ti I li ti t Ci it L l” 1995

9

Cornelius et. al: Shadow Transistors

in MOS Transistors: Testing Implications at Circuit Level” 1995.

Shadow Transistors Shadow Transistors

1 Insertion of additional transistors in

Main idea (1) ─ Parallel transistors

• 1. Insertion of additional transistors in

parallel to vulnerable transistors Shadow transistors (ST) Shadow transistors (ST)

8 10 Relative Delay

wo/ ST

100%

VDD/Vout

2 4 6 8

w/ ST

25% 50% 75%

w/ ST wo/ ST

2 ‐

RGC [kΩ] →

0% 25% ‐RGC [kΩ] →

For an Inverter 65nm BPTM

10

Cornelius et. al: Shadow Transistors

For an Inverter, 65nm-BPTM

Shadow Transistors Shadow Transistors

Main idea (2) ─ Thick gate oxides

2 Application of H Vt/To transistors with:

• 2. Application of H-Vt/To transistors with:

– Higher threshold voltage – Thicker gate oxide Thicker gate oxide

Less vulnerable to TDDB

0.15

MTTF

• x

t Δ

/ 0.22 /

10 4.81

H Vt To L Vt To

MTTF MTTF

− −

= =

0.22

10

• x

t Δ

Source: Srinivasan, “RAMP: A Model for Reliability Aware Microprocessor Design” St thi J “R li bilit Li it f th G t I l t i CMOS T h l ” MTTF – Mean Time To Failure

11

Cornelius et. al: Shadow Transistors

Stathis, J., “Reliability Limits for the Gate Insulator in CMOS Technology”

Shadow Transistors Shadow Transistors

Main idea (3) ─ Selective insertion

3 Selective insertion of shadow transistors in parallel to vulnerable

• 3. Selective insertion of shadow transistors in parallel to vulnerable

transistors:

– Component reliability depends on p y p Activity, state, temperature, size, fabrication …

Most vulnerable can be identified

Shadow transistors N tli t

• nly added in parallel

to most vulnerable devices. Netlist modification 12

Cornelius et. al: Shadow Transistors

Shadow Transistors Shadow Transistors

Main idea (3) ─ Selective insertion

3 Selective insertion of shadow transistors in parallel to vulnerable

• 3. Selective insertion of shadow transistors in parallel to vulnerable

transistors:

– Component reliability depends on

O A h

p y p Activity, state, temperature, size, fabrication …

Most vulnerable can be identified

• Estimation of stress factors
• Determination of components reliability

Our Approach

• Determination of components reliability
• Adding redundancy only at most vulnerable components

Shadow transistors N tli t Advantage: Lower area, power and delay penalty compared to complete redundancy or random insertion [Sri04]

Source: [Sri04] Sirisantana D&T 2004

• nly added in parallel

to most vulnerable devices. Netlist modification

Source: [Sri04] Sirisantana, D&T, 2004

13

Cornelius et. al: Shadow Transistors

Shadow Transistors Shadow Transistors

Main ideas ─ Discussion

Advantages

• Increased reliability in respect to TDDB
• H-Vt/To: Reliability increases by ~5x (for ∆tox = 0.15 nm)

g

Remarkable increase of system life time

Drawbacks

• Higher input capacity → higher delay and dynamic power dissipation
• Area increase

Drawbacks

Area increase

Remarks

• Only slight improvements for Gate-Drain/Source breakdown
• H-Vt/To has to be supported by technology

14

Cornelius et. al: Shadow Transistors

Shadow Transistors Shadow Transistors

Algorithm Estimation of logical Signal Estimation of logical Signal Probabilities (SP) Insertion of Shadow transistors where SP is lower (PMOS) than ( ) threshold value SPth or higher (NMOS) than 1 - SPth Modification of SPth Estimation of delay increase ∆td Modification of SPth depending on ∆td / MTTF and new Mean Time To Failure (MTTF) 15

Cornelius et. al: Shadow Transistors

Results Results

20% B

Improvement MTTF (L-Vt/To) ≈ 23 % additional transistors

15% gards TDDB 10% MTTF as reg 5% emnet of M 0% c17 c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 Improve Insertion of L‐Vt/To Shadow Transistors

• ur algorithm

random insertion

16

Cornelius et. al: Shadow Transistors

Results Results

20%

Performance Reduction (L-Vt/To) ≈ 23 % additional transistors

15% delay 10%

• f circuit's

5% Increase o 0% c17 c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 Insertion of L‐Vt/To Shadow Transistors

• ur algorithm

random insertion

17

Cornelius et. al: Shadow Transistors

Results Results

60% DB

Application of H-Vt/To-ST ≈ 23 % additional transistors

45% egards TDD 30% MTTF as re 15% vemnet of M 0% 432 499 880 1355 1908 2670 3540 5315 6288 7552 Improv c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 H‐Vt/To‐ST L‐Vt‐To‐ST

18

Cornelius et. al: Shadow Transistors

Results Results

250% DDB

Modification of Ccrit

200% regards TD 100% 150%

• f MTTF as

50%

• vemnet o

0% c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 Impro Insertion of H‐Vt/To Shadow Transistors SPth = 30 SPth = 55

19

Cornelius et. al: Shadow Transistors

Conclusion Conclusion

• System reliability decreases with shrinking technologies and rising

transistor count transistor count

• Increasing probability of Time-Dependent Dielectric Breakdown

(TDDB) (TDDB)

• Insertion of Shadow Transistors (ST) increases system lifetime

R k bl i t b li ti f t i t ith thi k

• Remarkable improvements by application of transistors with thick

gate-oxide S l ti i ti f ST i t d ff b t li bilit d

• Selective insertion of ST improves trade-off between reliability and

performance I t d t f d d t t i t b d t d b th

• Impact and amount of redundant transistors can be adapted by the

threshold value SPth

20

Cornelius et. al: Shadow Transistors

Thank you! Thank you!

claas cornelius@uni claas cornelius@uni rostock de rostock de claas.cornelius@uni claas.cornelius@uni-rostock.de rostock.de franksill@ufmg.br franksill@ufmg.br 21

Cornelius et. al: Shadow Transistors